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2. Parallel Loopback Design Examples
The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module.
Design Example | Designation | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|---|
DisplayPort SST parallel loopback without PCR | DisplayPort SST | RBR, HRB, HRB2, HBR3, UHBR10 | Simplex | Parallel without PCR |
DisplayPort SST parallel loopback with AXIS Video Interface | DisplayPort SST | RBR, HRB, HRB2, HBR3, UHBR10 | Simplex | Parallel with AXIS Video Interface |