Fronthaul Compression Intel® FPGA IP User Guide

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ID 709301
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Fronthaul Compression Intel® FPGA IP 2. Getting Started with the Fronthaul Compression Intel® FPGA IP 3. Fronthaul Compression IP Functional Description 4. Fronthaul Compression IP Registers 5. Fronthaul Compression Intel FPGA IPs User Guide Archive 6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide
1. About the Fronthaul Compression Intel® FPGA IP x
1.1. Fronthaul Compression Intel® FPGA IP Features 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support 1.3. Release Information for the Fronthaul Compression Intel® FPGA IP 1.4. Fronthaul Compression Performance and Resource Usage
2. Getting Started with the Fronthaul Compression Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP 2.2. Parameterizing the Fronthaul Compression IP 2.3. Generated IP File Structure
2.2. Parameterizing the Fronthaul Compression IP x
2.2.1. Fronthaul Compression IP Parameters
3. Fronthaul Compression IP Functional Description x
3.1. Fronthaul Compression IP Signals
1. About the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP
3. Fronthaul Compression IP Functional Description
4. Fronthaul Compression IP Registers
5. Fronthaul Compression Intel FPGA IPs User Guide Archive
6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide

2.2. Parameterizing the Fronthaul Compression IP

Quickly configure your custom IP variation in the IP Parameter Editor.
  1. Create an Quartus® Prime Pro Edition project in which to integrate your IP core.
    1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Intel Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
    2. Specify the device family that meets the speed grade requirements for the IP.
    3. Click Finish.
  2. In the IP Catalog, select Fronthaul Compression Intel FPGA IP.
    The New IP Variation window appears.
  3. Specify a top-level name for your new custom IP variation.
    The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
    Figure 2. Fronthaul Compression IP Parameter Editor
  5. Specify the parameters for your IP variation. Refer to Parameters for information about specific IP parameters.
  6. Click the Design Example tab and specify the parameters for your design example.
    Figure 3. Design Example Parameter Editor
  7. Click Generate HDL.
    The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate.
    The IP variation files generate according to your specifications.
  9. Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.

Section Content
Fronthaul Compression IP Parameters

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