Fronthaul Compression Intel® FPGA IP User Guide

ID 709301
Date 11/18/2024
Public

1.4. Fronthaul Compression Performance and Resource Usage

The resources of the IP targeting various devices
Table 4.  Fronthaul Compression Performance and Resource UsageAll entries are for compression and decompression data direction IP
Device IP ALMs Logic registers M20K
  Primary Secondary
Agilex 5 Block-floating point 14,903 26,337 5,948 0
µ-law 21,983 38,858 6,873 0
Block-floating point and µ-law 23,425 42,311 7,651 0
Block-floating point, µ-law, and extended IQ width 23,635 42,420 7,896 0
Agilex™ 7 Block-floating point 14,896 25,601 6,207 0
µ-law 22,036 38,658 7,008 0
Block-floating point and µ-law 23,481 41,935 7,850 0
Block-floating point, µ-law, and extended IQ width 23,666 41,978 7,789 0
Agilex 9 Block-floating point 14,906 25,598 6,304 0
µ-law 21,979 38,608 7,136 0
Block-floating point and µ-law 23,419 41,767 7,788 0
Block-floating point, µ-law, and extended IQ width 23,650 41,955 7,904 0
Arria 10 Block-floating point 12,459 16,316 5,226 0
µ-law 18,929 23,859 5,297 0
Block-floating point and µ-law 20,104 25,607 6,850 0
Block-floating point, µ-law, and extended IQ width 20,305 25,561 6,370 0
Stratix 10 Block-floating point 17,478 31,551 7,913 0
µ-law 24,902 44,102 7,795 0
Block-floating point and µ-law 26,726 49,224 8,862 0
Block-floating point, µ-law, and extended IQ width 26,948 49,305 8,916 0