Fronthaul Compression Intel® FPGA IP User Guide

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ID 709301
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Fronthaul Compression Intel® FPGA IP 2. Getting Started with the Fronthaul Compression Intel® FPGA IP 3. Fronthaul Compression IP Functional Description 4. Fronthaul Compression IP Registers 5. Fronthaul Compression Intel FPGA IPs User Guide Archive 6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide
1. About the Fronthaul Compression Intel® FPGA IP x
1.1. Fronthaul Compression Intel® FPGA IP Features 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support 1.3. Release Information for the Fronthaul Compression Intel® FPGA IP 1.4. Fronthaul Compression Performance and Resource Usage
2. Getting Started with the Fronthaul Compression Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP 2.2. Parameterizing the Fronthaul Compression IP 2.3. Generated IP File Structure
2.2. Parameterizing the Fronthaul Compression IP x
2.2.1. Fronthaul Compression IP Parameters
3. Fronthaul Compression IP Functional Description x
3.1. Fronthaul Compression IP Signals
1. About the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP
3. Fronthaul Compression IP Functional Description
4. Fronthaul Compression IP Registers
5. Fronthaul Compression Intel FPGA IPs User Guide Archive
6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide

2.2.1. Fronthaul Compression IP Parameters

Table 6.  Fronthaul Compression IP Parameters
Name Valid Values Description
Data direction

TX and RX,

TX only,

RX only

Select TX for compression; RX for decompression.
Compression method BFP, mu-Law, or BFP and mu-Law Select block floating-point, µ-law, or both.
Metadata width 0 (Disable Metadata Ports), 32, 64, 96, 128 (bit) Specify the bit width of the metadata bus (uncompressed data).
Enable extended IQ width On or off

Turn on for supported IqWidth of 8-bit to 16-bit.

Turn off for supported IqWidth of 9, 12, 14 and 16-bits.

O-RAN compliant On or off

Turn on to follow ORAN IP mapping for metadata port and assert metadata valid signal for each section header. The IP supports 128-bit width metadata only. The IP supports single section and multiple sections per packet. Metadata is valid at each section with metadata valid assertion.

Turn off so the IP uses metadata as passthrough conduit signals with no mapping requirement (e.g.: U-plane numPrb is assumed 0). The IP supports metadata widths of 0 (Disable Metadata Ports), 32, 64, 96, 128 bits. The IP supports single section per packet. Metadata is valid only once at the metadata valid assertion for each packet.

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