Fronthaul Compression Intel® FPGA IP User Guide

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ID 709301
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Fronthaul Compression Intel® FPGA IP 2. Getting Started with the Fronthaul Compression Intel® FPGA IP 3. Fronthaul Compression IP Functional Description 4. Fronthaul Compression IP Registers 5. Fronthaul Compression Intel FPGA IPs User Guide Archive 6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide
1. About the Fronthaul Compression Intel® FPGA IP x
1.1. Fronthaul Compression Intel® FPGA IP Features 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support 1.3. Release Information for the Fronthaul Compression Intel® FPGA IP 1.4. Fronthaul Compression Performance and Resource Usage
2. Getting Started with the Fronthaul Compression Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP 2.2. Parameterizing the Fronthaul Compression IP 2.3. Generated IP File Structure
2.2. Parameterizing the Fronthaul Compression IP x
2.2.1. Fronthaul Compression IP Parameters
3. Fronthaul Compression IP Functional Description x
3.1. Fronthaul Compression IP Signals
1. About the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP
3. Fronthaul Compression IP Functional Description
4. Fronthaul Compression IP Registers
5. Fronthaul Compression Intel FPGA IPs User Guide Archive
6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide

2.3. Generated IP File Structure

The Quartus® Prime Pro Edition software generates the following IP output file structure.
Table 7.  Generated IP Files
File Name Description
<your_ip>.ip

The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<your_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<your_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration.
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration.
<your_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime software.

<your_ip>.sopcinfo

Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios® V tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios® V tool chain include address map information for each agent relative to each host that accesses the agent. Different masters may have a different address map to access a particular agent component.

<your_ip>.csv Contains information about the upgrade status of the IP component.
<your_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use in Intel Quartus Prime Block Diagram Files (.bdf).
<your_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<your_ip>.v or <your_ip>.vhd HDL files that instantiate each submodule or child IP for synthesis or simulation.
mentor/

Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.

synopsys/vcs/

synopsys/vcsmx/

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX* simulation.

cadence/

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM* simulation.

aldec/

Contains a shell script rivierapro_setup.sh to setup and run an Aldec* simulation.

xcelium/

Contains a shell script xcelium_setup.sh and other setup files to set up and run an Xcelium* simulation.

submodules/ Contains HDL files for the IP submodules.
<child IP cores>/ For each generated child IP directory, Platform Designer generates synth/ and sim/ sub-directories.
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