Fronthaul Compression Intel® FPGA IP User Guide

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ID 709301
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Fronthaul Compression Intel® FPGA IP 2. Getting Started with the Fronthaul Compression Intel® FPGA IP 3. Fronthaul Compression IP Functional Description 4. Fronthaul Compression IP Registers 5. Fronthaul Compression Intel FPGA IPs User Guide Archive 6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide
1. About the Fronthaul Compression Intel® FPGA IP x
1.1. Fronthaul Compression Intel® FPGA IP Features 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support 1.3. Release Information for the Fronthaul Compression Intel® FPGA IP 1.4. Fronthaul Compression Performance and Resource Usage
2. Getting Started with the Fronthaul Compression Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP 2.2. Parameterizing the Fronthaul Compression IP 2.3. Generated IP File Structure
2.2. Parameterizing the Fronthaul Compression IP x
2.2.1. Fronthaul Compression IP Parameters
3. Fronthaul Compression IP Functional Description x
3.1. Fronthaul Compression IP Signals
1. About the Fronthaul Compression Intel® FPGA IP
2. Getting Started with the Fronthaul Compression Intel® FPGA IP
3. Fronthaul Compression IP Functional Description
4. Fronthaul Compression IP Registers
5. Fronthaul Compression Intel FPGA IPs User Guide Archive
6. Document Revision History for the Fronthaul Compression Intel® FPGA IP User Guide

3.1. Fronthaul Compression IP Signals

Connect and control the IP.
Table 8.  Clock and Reset Interface Signals
Signal Name Bitwidth Direction Description
tx_clk 1 Input

Transmitter clock.

Clock frequency is 390.625 MHz for 25 Gbps and 156.25MHz for 10 Gbps.

All transmitter interface signals are synchronous to this clock.

rx_clk 1 Input

Receiver clock.

Clock frequency is 390.625 MHz for 25 Gbps and 156.25MHz for 10 Gbps.

All receiver interface signals are synchronous to this clock.

csr_clk 1 Input

Clock for CSR interface.

Clock frequency is 100 MHz.

tx_rst_n 1 Input Active low reset for transmitter interface synchronous to tx_clk.
rx_rst_n 1 Input Active low reset for receiver interface synchronous to rx_clk.
csr_rst_n 1 Input Active low reset for CSR interface synchronous to csr_clk.
Table 9.  Transmit Transport Interface SignalsAll signal types are unsigned integer.
Signal Name Bitwidth Direction Description
tx_avst_source_valid 1 Output When asserted, indicates valid data is available on avst_source_data.
tx_avst_source_data 64 Output PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to previous section PRB field.
tx_avst_source_startofpacket 1 Output Indicates first byte of a frame.
tx_avst_source_endofpacket 1 Output Indicates last byte of a frame.
tx_avst_source_ready 1 Input When asserted, indicates the transport layer is ready to accept data. readyLatency = 0 for this interface.
tx_avst_source_empty 3 Output Specifies the number of empty bytes on avst_source_data when avst_source_endofpacket is asserted.
tx_udcomphdr_o 8 Output

User data compression header field.

Synchronous with tx_avst_source_valid.

Defines the compression method and IQ bit width for the user data in a data section.

  • [7:4] : udIqWidth
  • 16 for udIqWidth=0, otherwise equals udIqWidth e,g,:
    • 0000b means I and Q are each 16 bits wide;
    • 0001b means I and Q are each 1 bit wide;
    • 1111b means I and Q are each 15 bits wide
  • [3:0] : udCompMeth
    • 0000b - no compression
    • 0001b - block-floating point
    • 0011b - µ-law
    • others - reserved for future methods.
tx_metadata_o METADATA_WIDTH Output

Conduit signals passthrough and are not compressed.

Synchronous with tx_avst_source_valid.

Configurable bitwidth METADATA_WIDTH.

When you turn on O-RAN compliant, refer to Table 14.

When you turn off O-RAN compliant, this signal is only valid when tx_avst_source_startofpacket is 1.

tx_metadata_o does not have valid signal and uses tx_avst_source_valid to indicate valid cycle.

Not available when you select 0 Disable Metadata Ports for Metadata width.

Table 10.  Receive Transport Interface Signals No backpressure at this interface. Avalon streaming empty signal is not necessary in this interface because it is always zero.
Signal Name Bitwidth Direction Description
rx_avst_sink_valid 1 Input

When asserted, indicates valid data is available on avst_sink_data.

No avst_sink_ready signal at this interface.

rx_avst_sink_data 64 Input

PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to previous section PRB field.

rx_avst_sink_startofpacket 1 Input Indicates first byte of a frame.
rx_avst_sink_endofpacket 1 Input Indicates last byte of a frame.
rx_avst_sink_error 1 Input

When asserted in the same cycle as avst_sink_endofpacket, indicates the current packet is an error packet

rx_udcomphdr_i 8 Input

User data compression header field.

Synchronous with rx_metadata_valid_i.

Defines the compression method and IQ bit width for the user data in a data section.

  • [7:4] : udIqWidth
  • 16 for udIqWidth=0, otherwise equals udIqWidth. e.g.
    • 0000b means I and Q are each 16 bits wide;
    • 0001b means I and Q are each 1 bit wide;
    • 1111b means I and Q are each 15 bits wide
  • [3:0] : udCompMeth
    • 0000b - no compression
    • 0001b - block floating point
    • 0011b - µ-law
    • others - reserved for future methods.
rx_metadata_i METADATA_WIDTH Input

Uncompressed conduit signals passthrough.

rx_metadata_i signals are valid when rx_metadata_valid_i is asserted, synchronous with rx_avst_sink_valid.

Configurable bitwidth METADATA_WIDTH.

When you turn on O-RAN compliant, refer to Table 16.

When you turn off O-RAN compliant, this rx_metadata_i signal is only valid when both rx_metadata_valid_i and rx_avst_sink_startofpacket equal to 1.

Not available when you select 0 Disable Metadata Ports for Metadata width.

rx_metadata_valid_i 1 Input

Indicates that the headers (rx_udcomphdr_i and rx_metadata_i) are valid.

Synchronous with rx_avst_sink_valid.

Compulsory signal.

For O-RAN backward compatibility, assert rx_metadata_valid_i if the IP has valid common header IEs and repeated section IEs. On providing new section physical resource block (PRB) fields in rx_avst_sink_data, provide new section IEs in rx_metadata_i input together with rx_metadata_valid_i.

Table 11.  Transmit Application Interface Signals
Signal Name Bitwidth Direction Description
tx_avst_sink_valid 1 Input

When asserted, indicate valid PRB fields are available in this interface.

When operating in streaming mode, ensure no valid signal deassertion between start of packet and end of packet The only exception is when the ready signal deasserted.

tx_avst_sink_data 128 Input Data from application layer in network byte order.
tx_avst_sink_startofpacket 1 Input Indicate the first PRB byte of a packet
tx_avst_sink_endofpacket 1 Input Indicate the last PRB byte of a packet
tx_avst_sink_ready 1 Output When asserted, indicates the O-RAN IP is ready to accept data from application interface. readyLatency = 0 for this interface
tx_udcomphdr_i 8 Input

User data compression header field.

Synchronous with tx_avst_sink_valid.

Defines the compression method and IQ bit width for the user data in a data section.

  • [7:4] : udIqWidth
  • 16 for udIqWidth=0, otherwise equals udIqWidth. e.g.
    • 0000b means I and Q are each 16 bits wide;
    • 0001b means I and Q are each 1 bit wide;
    • 1111b means I and Q are each 15 bits wide
  • [3:0] : udCompMeth
    • 0000b - no compression
    • 0001b - block-floating point
    • 0011b - µ-law
    • others - reserved for future methods.
tx_metadata_i METADATA_WIDTH Input

Conduit signals passthrough and are not compressed.

Synchronous with tx_avst_sink_valid.

Configurable bitwidth METADATA_WIDTH.

When you turn on O-RAN compliant, refer to Table 14.

When you turn off O-RAN compliant, this signal only valid when tx_avst_sink_startofpacket equals to 1.

tx_metadata_i does not have valid signal and uses tx_avst_sink_valid to indicate valid cycle.

Not available when you select 0 Disable Metadata Ports for Metadata width.

Table 12.  Receive Application Interface SignalsNo backpressure at this interface.
Signal Name Bitwidth Direction Description
rx_avst_source_valid 1 Output

When asserted, indicates valid PRB fields are available in this interface.

No avst_source_ready signal at this interface.

rx_avst_source_data 128 Output Data to application layer in network byte order.
rx_avst_source_startofpacket 1 Output Indicates the first PRB byte of a packet
rx_avst_source_endofpacket 1 Output Indicates the last PRB byte of a packet
rx_avst_source_error 1 Output Indicates the packets contains error
rx_udcomphdr_o 8 Output

User data compression header field.

Synchronous with rx_avst_source_valid.

Defines the compression method and IQ bit width for the user data in a data section.

  • [7:4] : udIqWidth
  • 16 for udIqWidth=0, otherwise equals udIqWidth. e.g.
    • 0000b means I and Q are each 16 bits wide;
    • 0001b means I and Q are each 1 bit wide;
    • 1111b means I and Q are each 15 bits wide
  • [3:0] : udCompMeth
    • 0000b - no compression
    • 0001b - block floating point (BFP)
    • 0011b - µ-law
    • others - reserved for future methods.
rx_metadata_o METADATA_WIDTH Output

Uncompressed conduit signals passthrough.

rx_metadata_o signals are valid when rx_metadata_valid_o is asserted, synchronous with rx_avst_source_valid.

Configurable bitwidth METADATA_WIDTH.

When you turn on O-RAN compliant, refer to Table 15.

When you turn off O-RAN compliant, rx_metadata_o is only valid when rx_metadata_valid_o equals 1.

Not available when you select 0 Disable Metadata Ports for Metadata width.

rx_metadata_valid_o 1 Output

Indicates that the headers (rx_udcomphdr_o and rx_metadata_o) are valid.

rx_metadata_valid_o is asserted when rx_metadata_o is valid, synchronous with rx_avst_source_valid.

Table 13.  CSR Interface Signals
Signal Name Bit Width Direction Description
csr_address 16 Input Configuration register address.
csr_write 1 Input Configuration register write enable.
csr_writedata 32 Input Configuration register write data.
csr_readdata 32 Output Configuration register read data.
csr_read 1 Input Configuration register read enable.
csr_readdatavalid 1 Output Configuration register read data valid.
csr_waitrequest 1 Output Configuration register wait request.

Metadata Mapping for O-RAN Backward Compatibility

Table 14.  tx_metadata_i 128-bit input
Signal Name Bitwidth Direction Description Metadata Mapping
Reserved 16 Input Reserved. tx_metadata_i[127:112]
tx_u_numberofsection 8 Input U-plane number of section for streaming mode. tx_metadata_i[119:112]
tx_u_prbusize 16 Input PRB U-plane IQ data size in bytes for streaming mode. tx_metadata_i[111:96]
tx_u_seq_id 16 Input SeqID of the packet, which is extracted from eCPRI transport header. tx_metadata_i[95:80]
tx_u_pc_id 16 Input PCID for eCPRI transport and RoEflowId for radio over ethernet (RoE) transport. tx_metadata_i[79:64]
Reserved 4 Input Reserved. tx_metadata_i[63:60]
tx_u_dataDirection 1 Input

gNB data direction.

Value range: {0b=Rx (i.e. upload), 1b=Tx (i.e. download)}

 tx_metadata_i[59]
tx_u_filterIndex 4 Input

Defines an index to the channel filter to be used between IQ data and air interface.

Value range: {0000b-1111b}

 tx_metadata_i[58:55]
tx_u_frameId 8 Input

A counter for 10 ms frames (wrapping period 2.56 seconds), specifically frameId= frame number modulo 256.

Value range: {0000 0000b-1111 1111b}

 tx_metadata_i[54:47]
tx_u_subframeId 4 Input

A counter for 1 ms subframes within 10 ms frame.

Value range: {0000b-1111b}

 tx_metadata_i[46:43]
tx_u_slotID 6 Input

This parameter is the slot number within a 1 ms subframe. All slots in one subframe are counted by this parameter.

Value range: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Reserved}

tx_metadata_i[42:37]
tx_u_symbolid 6 Input

Identifies a symbol number within a slot.

Value range: {00 0000b-11 1111b}

 tx_metadata_i[36:31]
tx_u_sectionId 12 Input

The sectionID maps U-plane data sections to the corresponding C-plane message (and Section Type) associated with the data.

Value range: {0000 0000 0000b-1111 1111 1111b}

 tx_metadata_i[30:19]
tx_u_rb 1 Input

Resource block indicator.

Indicate if every resource block is used or every other resource block is used.

Value range: {0b=every resource block used; 1b=every other resource block used}

 tx_metadata_i[18]
tx_u_startPrb 10 Input

The starting PRB of a user plane data section.

Value range: {00 0000 0000b-11 1111 1111b}

 tx_metadata_i[17:8]
tx_u_numPrb 8 Input

Define the PRBs where the user plane data section is valid.

Value range: {0000 0001b-1111 1111b, 0000 0000b = all PRBs in the specified subcarrier spacing (SCS) and carrier bandwidth }

tx_metadata_i[7:0]
tx_u_udCompHdr 8 Input

Define the compression method and IQ bit width of the user data in a data section.

Value range: {0000 0000b-1111 1111b}

 N/A (tx_udcomphdr_i)
Table 15.  rx_metadata_valid_i/o
Signal Name Bitwidth Direction Description Metadata Mapping
rx_sec_hdr_valid 1 Output

When rx_sec_hdr_valid is 1, the U-plane section data fields are valid.

Common header IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_sink_u_startofpacket and avst_sink_u_valid.

Repeated section IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_sink_u_valid.

On providing new section PRB fields in avst_sink_u_data, provide new section IEs with rx_sec_hdr_valid asserted.

rx_metadata_valid_o
Table 16.  rx_metadata_o 128-bit output
Signal Name Bitwidth Direction Description Metadata Mapping
Reserved 32 Output Reserved. rx_metadata_o[127:96]
rx_u_seq_id 16 Output SeqID of the packet, which is extracted from eCPRI transport header. rx_metadata_o[95:80]
rx_u_pc_id 16 Output PCID for eCPRI transport and RoEflowId for RoE transport rx_metadata_o[79:64]
reserved 4 Output Reserved. rx_metadata_o[63:60]
rx_u_dataDirection 1 Output

gNB data direction.

Value range: {0b=Rx (i.e. upload), 1b=Tx (i.e. download)}

rx_metadata_o[59]
rx_u_filterIndex 4 Output

Defines an index to the channel filter to use between IQ data and air interface.

Value range: {0000b-1111b}

 rx_metadata_o[58:55]
rx_u_frameId 8 Output

A counter for 10 ms frames (wrapping period 2.56 seconds), specifically frameId= frame number modulo 256.

Value range: {0000 0000b-1111 1111b}

rx_metadata_o[54:47]
rx_u_subframeId 4 Output

A counter for 1ms subframes within 10 ms frame.

Value range: {0000b-1111b}

rx_metadata_o[46:43]
rx_u_slotID 6 Output

The slot number within a 1ms subframe. All slots in one subframe are counted by this parameter.

Value range: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Reserved}

rx_metadata_o[42:37]
rx_u_symbolid 6 Output

Identifies a symbol number within a slot.

Value range: {00 0000b-11 1111b}

rx_metadata_o[36:31]
rx_u_sectionId 12 Output

The sectionID maps U-plane data sections to the corresponding C-plane message (and Section Type) associated with the data.

Value range: {0000 0000 0000b-1111 1111 1111b}

rx_metadata_o[30:19]
rx_u_rb 1 Output

Resource block indicator.

Indicates if every resource block is used or every other resource is used.

Value range: {0b=every resource block used; 1b=every other resource block used}

rx_metadata_o[18]
rx_u_startPrb 10 Output

The starting PRB of a user plane data section.

Value range: {00 0000 0000b-11 1111 1111b}

rx_metadata_o[17:8]
rx_u_numPrb 8 Output

Defines the PRBs where the user plane data section is valid.

Value range: {0000 0001b-1111 1111b, 0000 0000b = all PRBs in the specified SCS and carrier bandwidth }

rx_metadata_o[7:0]
rx_u_udCompHdr 8 Output

Defines the compression method and IQ bit width of the user data in a data section.

Value range: {0000 0000b-1111 1111b}

N/A (rx_udcomphdr_o)
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