To read device information:

1. Click Hardware Setup to select the hardware setup to use for debugging.
2. Click Load Device and select a device from the drop-down list if more than one device exists in the hardware setup.
3. Click Device Info for device information reading.
   Note: The Device Info tab is disabled if the selected device is not supported.
4. Click Read to read device information from the selected device.
   • Configuration Status:
     • MSEL
     • CONF_DONE
     • nSTATUS
     • nCE
     • nCONFIG
     • DCLK
   • Key Verify Register (Significant Bits Only) which is only available for 20 nm devices.
     Note: Refer to Key Verify Register Description for more details on Key Verify Register description.
   • Error Message Register (EMR) to identify any error detection cyclic redundancy check (EDCRC) failure location and error type. If the FPGA is unconfigured or the EDCRC is not enabled, the EMR value in the table may be inaccurate.
     Note: Refer to Error Type Table for 20 nm Devices and Error Type Table for 28 nm Devices for more details on error types.
5. Click Pulse nCONFIG to force the device to exit user mode. Reconfiguration is then required.
   Figure 5. Device Information for Legacy Devices

   Table 3.  Key Verify Register Description

   Key Verify Register	Description
   [0]: Volatile Key	This bit is set when a volatile key has been successfully programmed into the device.
   [1]: Attempt Non-volatile Key Programming	This bit is set to indicate that an attempt was made to burn a non-volatile key in the OTP fuses.
   [2]: Disable Non-volatile Key	This bit is set to disable use of the non-volatile key.
   [3]: Non-volatile Key	This bit is set to indicate that a non-volatile key has been successfully burnt into the OTP fuses.
   [4]: Tamper Protection	This bit is set to indicate that the FPGA is in Tamper Protection mode with either Non-volatile or Volatile key.
   [6]: Volatile Key Lock	This bit is set to prevent the volatile key from being reprogrammed from external JTAG.
   [11]: Force Configuration from HPS only	This bit is set when configuration is allowed from HPS only.
   [12]: External JTAG Bypass	This bit is set to indicate that external JTAG is disabled.
   [13]: HPS JTAG Bypass	This bit is set to indicate that HPS JTAG is disabled.
   [14]: Disable Partial Reconfiguration and Scrubbing	This bit is set to indicate that external PR and external scrubbing (including HPS PR and HPS scrubbing) are disabled.
   [15]: Disable Volatile Key	This bit is set to indicate that the volatile key is disabled.
   [17]: Disable Key Related JTAG Instructions	This bit is set to indicate that external JTAG access to all key related JTAG instructions is disabled.
   [18]: JTAG Secure Mode	This bit is set to indicate that only mandatory JTAG instructions are allowed to be externally accessed.
   [20]: Volatile Key Clear	This bit is set when the volatile key is successfully cleared from the device.

   Table 4.  Error Type Table for 20 nm Devices

   Frame/Column	Bit	Error Type
   Frame-based [2:0]	b000	No error
   Frame-based [2:0]	b001	Single-bit error
   Frame-based [2:0]	b01X	Double-adjacent error
   Frame-based [2:0]	b111	Un-correctable error
   Column-based [2:0]	b000	No error
   Column-based [2:0]	b001	Single-bit error
   Column-based [2:0]	b01X	Double-adjacent error in a same frame
   Column-based [2:0]	b10X	Double-adjacent error in a different frame
   Column-based [2:0]	b110	Double-adjacent error in a different frame
   Column-based [2:0]	b111	Un-correctable error

   Table 5.  Error Type Table for 28 nm Devices

   Bit	Error Type
   b0000	No error
   b0001	Single-bit error
   b0010	Double-adjacent error
   b1111	Un-correctable error