F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

5.4. SYSREF Sampling

You can choose to enable continuous SYSREF sampling or a single SYSREF detection.

The software logic programs the clock cleaner to the SPI to enable SYSREF generation. To resample SYSREF , the software logic writes to the SYSREF_CTRL registers to enable either a continuous sampling or a single detection. If both bits are enabled, continuous sampling takes precedence.

You may want to disable SYSREF sampling after some time. Disabling SYSREF sampling also disables the continuous sampling mode, and subsequently programs the clock cleaner to disable SYSREF output.

Consider one of the following recommendations to configure the SYSREF resampling flow:

  1. Set the sysref_singledet, sysref_alwayson, and sysref_lemc_err_en_reinit register bits to 1.
    • If a new SYSREF edge is detected, the F-Tile JESD204C IP clears the sysref_singledet bit and automatically starts a link reinitialization.
    • All the Avalon® streaming interface signals return to default state.
    • The LEMC block resets to reflect the newly detected SYSREF edge.
    • All the Avalon® streaming interface signals are active again based on a new LEMC data.
    • If LEMC error interrupt is enabled, the F-Tile JESD204C needs to service and clear the error.
  2. Set the sysref_singledet bit to 1 and sysref_alwayson bit to 0.
    • If a new SYSREF edge is detected, the F-Tile JESD204C IP clears the sysref_singledet bit, but no automatic start of link reinitialization.
    • All the Avalon® streaming interface signals remain active.
    • The LEMC block resets to reflect the newly detected SYSREF edge.
      • In the TX IP, the egress sync header (SH) adjusts as LEMC undergoes realignment to the new SYSREF edge. The corresponding RX (that receives the adjusted SH) may subject to SH-related errors.
      • In the RX IP, the ingress Avalon® streaming data does not get affected because the change of LEMC does not impact the already streaming data. However, the link loses its deterministic latency characteristic. To restore the deterministic latency behavior, a link reinitialization is required.
    • You must set the link_reinit bit to 1 after sysref_singledet clears to start a link reinitialization.
    • All the Avalon® streaming interface signals return to default state, and get reactivated based on a new LEMC data.
To better handle potential race conditions between the assertion of the link_reinit bit (through user-specified or auto reinitialization) and the assertion of the sysref_singledet bit, the IP imposes the following behavior:
  • For TX core: If the the link_reinit bit asserts), the Avalon® streaming interface deactivates. After the link reinitialization is complete, the Avalon® streaming interface gets activated only when the sysref_singledet deasserts.
  • For RX core: If the the link_reinit bit asserts, the Avalon® streaming interface deactivates. After the link reinitialization is complete, the Avalon® streaming interface gets activated only when the sysref_singledet deasserts, and SH (j204c_rx_sh_lock) and EMB (j204c_rx_emb_lock) have achieved lock.
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