F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

3.2. Local Extended Multiblock Clock

The F-Tile JESD204C IP uses the Extended Multiblock Clock (LEMC) as a common timing reference to support multidevice configuration.

LEMC is an internal clock that aligns the boundaries of the extended multiblocks between lanes. In deterministic latency devices, LEMC aligns the boundaries to an external reference, for example, SYSREF. The use of LEMC is mandatory in Subclass 1 modes but optional in Subclass 0 modes.

The F-Tile JESD204C IP implements LEMC as a counter that increments in link clock counts, and depends on the Multiblocks in an extended multiblock (E) parameter. The extended multiblock is a container of a number of multiblocks.

The E parameter depends on these two factors:

  • The parameter must allow an integer of F within an extended multiblock. For example, if F=3, 32 multiblocks contain 256 octets (32x64/8). 256 octets is not divisible by F=3. So, for F=3, the minimum E is 3.
  • E must be larger than the maximum possible delay variation across any two lanes of a link.

In Subclass 1 deterministic latency system, SYSREF is distributed to the devices to be aligned in the system. The SYSREF signal resets the internal LEMC clock edge when the sampled SYSREF rising edge transitions from 0 to 1.

The F-Tile JESD204C IP does not use the device clock directly to sample SYSREF because of the source synchronous signaling of SYSREF with respect to the device clock sampling from the clock chip. The IP uses the link clock to sample SYSREF. The PLL that provides the link clock or frame clock must be in normal mode to phase-compensate the link clock to the device clock.

You can program a single or multiple sampling of SYSREF through the F-Tile JESD204C control and status registers.

  • A single sampling SYSREF does not detect SYSREF period errors.
  • A continuous sampling mode detects SYSREF period errors.

In most converter device systems, disable SYSREF sampling if there are no errors, and begin link operation with a link reinitialization request.


Section Content
LEMC Counter

Level Two Title