F-Tile JESD204C Intel® FPGA IP User Guide

Download PDF
ID 691272
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

5.1.2. F-Tile JESD204C RX Reset Sequence

Figure 11.  F-Tile JESD204C RX Reset Sequence

The descriptions below correspond to the Figure 11:

  1. The user logic asserts the F-Tile JESD204C IP and configuration reset to the F-Tile JESD204C IP RX, j204c_rx_avs_rst_n = 1, j204c_rx_rst_n = 0, and reconfig_xcvr_reset = 1.
    Note: If you assert j204c_rx_avs_rst_n and reconfig_xcvr_reset, j204c_rx_rst_n is required to be asserted as well. You can opt to assert j204c_rx_rst_n without asserting j204c_rx_avs_rst_n and reconfig_xcvr_reset.
  2. The user logic deasserts j204c_rx_avs_rst_n and reconfig_xcvr_reset and perform configurations of the PHY and IP. At the same, wait for IOPLL to lock.
  3. After all relevant PHY channels are fully in reset, the IP core asserts j204c_rx_rst_ack_n to the user logic. Knowing the relevant channels are in proper reset states, the user logic can release the reset to the IP core when possible (j204c_rx_rst_n = 1). Use j204c_rx_rst_ack_n as an indicator to deassert j204c_rx_rst_n = 1.
  4. The user logic deasserts the IP reset (j204c_rx_rst_n = 1).
  5. The IP asserts j204c_rx_avst_valid = 1 when alignment and deskew is achieved, and deskew is complete. The F-Tile JESD204C RX IP core is operational.
  6. At any time when you require a reset to the MAC and PHY, you must wait for j204c_rx_rst_ack_n = 1. Assertion of j204c_rx_rst_n = 0 resets the MAC and PHY in the IP core.
  7. The IP core asserts j204c_rx_rst_ack_n = 0 to indicate that reset sequence is complete.
Level Two Title