F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 6/27/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

7.2. Receiver Signals

Table 20.  Top-level Receiver IP Core Signals

Signal

Width

Direction

Description

JESD204C RX Clocks and Resets
j204c_pll_refclk

1

Input

Transceiver reference clock signal.

j204c_syspll_div2_clk 1 Output System PLL divided by 2 clock.
j204c_rxlink_clk

1

Input

This clock is equal to the RX data rate divided by 66. Generated from the same PLL as rxframe_clk.

j204c_rxlclk_ctrl 1 Input Generated from the same PLL as rxlink_clk and rxframe_clk. This clock control acts as a phase information for j204c_rxlink_clk to handle CDC between j204c_rxlink_clk and j204c_rxframe_clk. This clock control is tied to 1 because j204c_rxlink_clk is always same or 2 times slower than j204c_rxframe_clk. Every j204c_rxlink_clk positive clock edge is aligned to j204c_rxframe_clk positive clock edge.
j204c_rxframe_clk

1

Input

This signal is synchronous with rxlink_clk. Frequency is equal or multiplied by 2 of rxlink_clk. Generated from the same PLL as rxlink_clk.

j204c_rxfclk_ctrl

1

Input

Generated from the same PLL as j204c_rxlink_clk and j204c_rxframe_clk. This clock acts as a phase information of j204c_rxframe_clk to handle CDC crossing from j204c_rxframe_clk to j204c_rxlink_clk. If FCLK_MULP = 1, this clock is tied to 1 because every j204c_rxframe_clk positive clock edge is aligned to the j204c_rxlink_clk positive clock edge. However, if FCLK_MULP=2, this signal pulses high for every j204c_rxframe_clk period which has the positive clock edge aligned to the j204c_rxlink_clk positive clock edge.
j204c_rx_avs_clk

1

Input

Avalon® memory-mapped interface clock.

j204c_rx_rst_ack_n 1 Output Asynchronous signal.

Acknowledgment indicator of the state of j204c_rx_rst_n.

reconfig_xcvr_clk

1

Input

Transceiver reconfiguration clock. During duplex mode, both TX and RX share the same reconfiguration pins.
sysclk 1

Input

System PLL clock connected to external system PLL. The F-Tile system clock frequency is user-defined. The system clock frequency is greater or equal to the native clock frequency.
j204c_rx_rst_n

1

Input

Active-low asynchronous reset signal for MAC LL, PHY, and TL.
j204c_rx_avs_rst_n 1

Input

Active-low asynchronous reset signal for RX Avalon® memory-mapped interface.

This signal deasserts synchronously to rx_avs_clk.

reconfig_xcvr_reset 1 Input PMA Avalon® memory-mapped interface reset.

Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins.

Intel recommends that you tie this signal to tx_avs_rst_n.

Signal

Width

Direction

Description

Transceiver Interface
rx_serial_data

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

rx_serial_data_n

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

reconfig_xcvr_read

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

reconfig_xcvr_write

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

reconfig_xcvr_address

log2(L) +18

Input

Each transceiver lanes address is 18 bits wide. The upper bits are lane select.

This signal is synchronous with reconfig__xcvr_clk.

reconfig_xcvr_readdata

32

Output

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

reconfig_xcvr_writedata

32

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

reconfig_xcvr_byteenable 4 Input

Byte enable signal. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access.

This signal is synchronous with reconfig__xcvr_clk.

Signal

Width

Direction

Description

JESD204C RX MAC Avalon® Memory-Mapped Interface
j204c_rx_avs_chipselect

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_address

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_writedata

32

Input

32-bit data for write transfers.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_read

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_rx_avs_readdata[31:0] signal to be in use.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_write

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_rx_avs_writedata[31:0] signal to be in use.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_readdata

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

This signal is synchronous with rx_avs_clk.

j204c_rx_avs_waitrequest

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The F-Tile JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

This signal is synchronous with rx_avs_clk.

Signal

Width

Direction

Description

JESD204C RX MAC Avalon® Streaming Interface (Data Channel)
j204c_rx_avst_data

M*S*N*WIDTH_MULP

Output

The minimum data width = M*S*N. This signal is synchronous to rxframe_clk. Indicates the converter samples that is processed by TL.

This signal indicates a 64-bit user data (per lane) at rxlink_clk clock rate, where 8 octets are packed into a 64-bit data width per lane. The data format is big endian.

If L=1 and M*S*N*WIDTH_MULP=64, the first octet is located at bit[63:56], followed by bit[55:48], and the last octet is bit[7:0]. If more than one lane is instantiated, Lane 0 data is always located in the upper 64-bit. Data lane L’s data is located at bit[63:0], with the first octet position for lane L is at bit[63:56].

j204c_rx_avst_control

M*S*WIDTH_MULP*CS

Output

Control bits that were inserted as part of CS parameter.

This signal is synchronous to rxframe_clk.

j204c_rx_avst_valid

1

Output

Indicates whether the data to the application layer is valid or invalid. The Avalon® streaming sink interface in the RX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_rx_avst_ready signal is asserted.

  • 0—data is invalid
  • 1—data is valid

This signal is synchronous to rxframe_clk.

j204c_rx_avst_ready

1

Input

Indicates that the Avalon® streaming sink interface in the application layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

This signal is synchronous to rxframe_clk.

j204c_rx_crc_err

L

Output

Indicates when CRC error is detected on previous multiblock.

This signal is synchronous to rxlink_clk.

Signal

Width

Direction

Description

JESD204C RX MAC Command (Command Channel)
j204c_rx_cmd_data

L*6

L*18

Output

Indicates a 6/18-bit user command (per lane) at rxlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

This signal is synchronous to rxlink_clk.

If CRC-12 is enabled, the width is L*6. If standalone command channel, the width is L*18.

j204c_rx_cmd_valid

1

Output

This signal is synchronous to rxlink_clk.

Indicates whether the command from the link layer is valid or invalid when the j204c_rx_cmd_ready signal is asserted.

  • 0—data is invalid
  • 1—data is valid
j204c_rx_cmd_ready

1

Input

This signal is synchronous to rxlink_clk.

Indicates that the transport or application layer is ready to accept command. The application layer interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

j204c_rx_cmd_par_err

1, L

Output

This signal is synchronous to rxlink_clk.

Indicates when parity error is detected.

  • Width is 1 if you enable single lane mode.
  • Width is L if you disable single lane mode.

Signal

Width

Direction

Description

JESD204C Interface
j204c_rx_sysref

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

j204c_rx_sh_lock

1

Output

Indicates sync header lock.

This signal is synchronous to rxlink_clk.

j204c_rx_emb_lock

1

Output

Indicates EMB lock.

This signal is synchronous to rxlink_clk.

j204c_rx_dev_emblock_align 1

Output

Indicates that all EMB blocks of all the lanes in a F-Tile JESD204C IP instance are aligned.

Note: Applicable only when you turn on the Multilink mode parameter.
j204c_rx_dev_lane_align

1

Output

Indicates that all lanes in a F-Tile JESD204C IP instance are aligned.

j204c_rx_alldev_emblock_align 1

Input

For multilink synchronization, input the j204c_rx_dev_emblock_align signals from all the F-Tile JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

Note: Applicable only when you turn on the Multilink mode parameter.
j204c_rx_alldev_lane_align

1

Input

For multi-device synchronization, input the j204c_rx_dev_lane_align signals from all the F-Tile JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

For single device, connect the j204c_rx_dev_lane_align signal back to this signal.

This signal is synchronous to rxlink_clk.

Signal

Width

Direction

Description

JESD204C RX MAC CSR
j204c_rx_csr_l

4

Output

Indicates the number of active lanes for the link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_f

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_m

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_cs

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

j204c_rx_csr_n

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_np

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_s

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

j204c_rx_csr_hd

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_cf

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_e 8

Output

LEMC period. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

j204c_rx_csr_testmode

2

Output

This signal is synchronous to rx_avs_clk.

  • 0—No test mode
  • 1—TX2RX loopback mode enabled (66 bit loopback)
  • 2—TX2RX_GB loopback mode enabled (64 bit loopback)
  • 3—Invalid

Signal

Width

Direction

Description

JESD204C RX MAC Out-of-band (OOB)
j204c_rx_int

1

Output

Asynchronous signal.

Interrupt pin for the F-Tile JESD204C Intel® FPGA IP.

Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

j204c_tx2rx_lbdata L*66

Input

Input and multiplexed with RX gearbox output when TX2RX loopback mode is enabled. This is to be connected to TX IP in duplex setup (same signal name) for TX2RX loopback function.

If L>0, MSB of this bus is mapped to Lane 0. LSB is mapped to Lane L-1.

This signal is synchronous to rxlink_clk.

j204c_tx2rx_lbdata_gb L*64 Input

This input is valid when the 66/64 gearbox is available.

Synchronous to rxphy_clk or sysclk.

Multiplexed with the RX gearbox input when the TX2RX_GB loopback mode is enabled to connect to TX IP in the duplex setup (same signal name) for the TX2RX loopback function.

If L > 0, MSB of this bus is mapped to Lane 0. LSB is mapped to Lane L-1.
j204c_tx2rx_lbdata_gb_valid L Output Assert to indicate j204c_tx2rx_lbdata_gb is valid. LSB is mapped to Lane 0, MSB is mapped to Lane L-1.

This signal is synchronous to rxphy_clk or sysclk.

Note: For information about the transceiver PHY signals, refer to the Signal and Port Reference section in the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
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