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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Stratix® 10 DisplayPort SST TX-only or RX-only Design Features
2.3. Design Components
2.4. Clocking Scheme
2.5. Interface Signals and Parameters
2.6. Hardware Setup
2.7. Simulation Testbench
2.8. DisplayPort Transceiver Reconfiguration Flow
2.9. Transceiver Lane Configurations
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2. Parallel Loopback Design Examples
The DisplayPort Intel® FPGA IP Parallel Loopback design examples demonstrates parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Design Example | Designation | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|---|
DisplayPort SST TX-only | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | - |
DisplayPort SST RX-only | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | - |
DisplayPort SST parallel loopback with PCR | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel with PCR |
DisplayPort SST parallel loopback without PCR | DisplayPort SST | HBR3, HBR2, HBR, and RBR | Simplex | Parallel without PCR |
Section Content
Intel Stratix 10 DisplayPort SST Parallel Loopback Design Features
Intel Stratix 10 DisplayPort SST TX-only or RX-only Design Features
Design Components
Clocking Scheme
Interface Signals and Parameters
Hardware Setup
Simulation Testbench
DisplayPort Transceiver Reconfiguration Flow
Transceiver Lane Configurations