AN 825: Partially Reconfiguring a Design: on Intel® Stratix® 10 GX FPGA Development Board

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ID 683880
Date 12/07/2020
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Document Table of Contents x
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 825: Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board

Step 3: Allocating Placement and Routing Region for a PR Partition

For every base revision you create, the PR design flow places the corresponding persona core in your PR partition region. To locate and assign the PR region in the device floorplan for your base revision:
  1. Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears on the Logic Lock Regions Window.
  2. Your placement region must enclose the blinking_led logic. Select the placement region by locating the node in Chip Planner. Right-click the u_blinking_led region name in the Logic Lock Regions Window and click Locate Node > Locate in Chip Planner.

    The u_blinking_led region is color-coded.

    Figure 4. Chip Planner Node Location for blinking_led
  3. In the Logic Lock Regions window, specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) co-ordinates as (169 410), specify the Origin as X169_Y410. The Intel® Quartus® Prime software automatically calculates the (X2 Y2) co-ordinates (top-right) for the placement region, based on the height and width you specify.
    Note: This tutorial uses the (X1 Y1) co-ordinates - (169 410), and a height and width of 20 for the placement region. Define any value for the placement region. Ensure that the region covers the blinking_led logic.
  4. Enable the Reserved and Core-Only options.
  5. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
  6. Select Fixed with expansion for the Routing type. Selecting this option automatically assigns an expansion length of 1.
    Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
    Figure 5.  Logic Lock Regions Window
Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning: 
set_instance_assignment -name PLACE_REGION "X169 Y410 X188 Y429" -to \
        u_blinking_led 
set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
        u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
        u_blinking_led
set_instance_assignment -name ROUTE_REGION "X168 Y409 X189 Y430" -to \
        u_blinking_led
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