F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 6/26/2023
Public

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5.8.1. F-tile Interface Planner Usage Example

The design used includes two 25.78125 Gbps NRZ PMA Direct FGT PMA lanes, with a throughput of 51.5625 Gbps, and with the system PLL datapath clocking mode.
The example illustrates the steps you need to follow to use the Tile Interface Planner tool in the Intel® Quartus® Prime software.
  1. Run the Design Analysis substep under Support-Logic Generation in the compilation flow window of Intel® Quartus® Prime software.
  2. Click the Tile Interface Planner tool icon on the right side of the compilation flow window to launch the tool as shown in the following figure.
    Figure 109. Launching the Tile Interface Planner
  3. When the tool successfully launches, click on Update Plan under the Flow pane on the left side to load any saved plans and begin tile interface planning as shown in the following figure.
    Figure 110. Update Plan in the Tile Interface Planner
  4. Navigate to the Plan tab to visualize the design elements and the tile floorplan. Right click on any of the design elements to see the available legal locations in the right pane for that element, and double click on one of the locations to place the IP element as shown in the following figure.
    Figure 111. Place Elements in the Tile Interface Planner
  5. Right click on any of the design elements to make them fixed and to save the placement as shown in the following figure.
    Figure 112. Save Placement in the Tile Interface Planner
  6. Click on Save Assignments in the Flow pane on the left, to save the placements as .qsf assignments as shown in the following figure.
    Figure 113. Save Assignments in the Tile Interface Planner
  7. Navigate to the Assignments tab, to see the saved .qsf assignments for the design as shown in the following figure.
    Figure 114. View Assignments in the Tile Interface Planner