F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 6/26/2023
Public

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3.11.6. Accessing Configuration Registers

This section summarizes how to access the configuration registers listed in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map. You can use the detailed information to access the PMA and FEC Direct PHY Soft CSR registers, FHT PMA registers, and FGT PMA registers. In this section, the terminology offset address refers to the address of the configuration registers in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map.

In order to access all the configuration registers, it is recommended to set the Avalon® memory-mapped interface as shown in the following figure.
Figure 89. Recommended Avalon Memory-Mapped Interface Settings