F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.3.1.2. FHT Receiver PMA Architecture

The receiver recovers the clock information from the received serial data, deserializes the high-speed serial data, and creates a parallel data stream for either the receiver Ethernet hard IP, FEC block, or FPGA core.