F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1. FHT PMA Architecture

The FHT PMA supports the following parallel data widths.

Table 12.  FHT PMA Data Widths
PMA Width Modulation Supported Data Rates
32 NRZ

24 - 29 Gbps

64 NRZ and PAM4 48 - 58 Gbps
128 PAM4 96 - 116 Gbps
Figure 39. FHT PMA Block DiagramLegend:
  • analog-to-digital converter (ADC)
  • clock data recovery (CDR)
  • continuous time-linear equalization (CTLE)
  • decision feedback equalization (DFE)
  • digital-to-analog converter (DAC)
  • feed forward equalization (FFE)
  • phase generator (PhG)
  • serial-in, parallel-out (SIPO)
  • transmitter buffer (TX Buffer)
  • transmitter equalizer (TX EQ)
  • voltage gain amplifier (VGA)