Error Message Register Unloader Intel FPGA IP Core User Guide

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ID 683866
Date 5/23/2018
Public
Document Table of Contents
Document Table of Contents x
1. Error Message Register Unloader Intel® FPGA IP Core User Guide
1. Error Message Register Unloader Intel® FPGA IP Core User Guide x
1.1. Features 1.2. IP Core Device Support 1.3. Resource Utilization and Performance 1.4. Functional Description 1.5. Parameter Settings 1.6. Installing and Licensing Intel® FPGA IP Cores 1.7. Customizing and Generating IP Cores 1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
1.4. Functional Description x
1.4.1. Error Message Register 1.4.2. Signals 1.4.3. Timing
1.4.3. Timing x
1.4.3.1. IP Timing Behavior ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices) 1.4.3.2. All Other Device Timing
1.7. Customizing and Generating IP Cores x
1.7.1. IP Catalog and Parameter Editor 1.7.2. The Parameter Editor 1.7.3. Specifying IP Core Parameters and Options 1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors)
1.7.3. Specifying IP Core Parameters and Options x
1.7.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors) x
1.7.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1. Error Message Register Unloader Intel® FPGA IP Core User Guide

1.4.2. Signals

Table 3.   Error Message Register Unloader Signals
Signal Width Direction Description
clock 1 Input Input clock signal.
reset 1 Input Active-high logic reset signal.
emr_read 1 Input Optional. This active-high signal initiates rereading the current EMR content. The EMR content updates when the device detects a new error. The EMR contains the error until a new error is detected, even if internal or external scrubbing corrects the error.
crcerror 1 Output Indicates detection of a CRC error. This signal synchronizes to the clock port of the Error Message Register Unloader IP core.
crcerror_pin 1 Output Connect this signal to the CRC_Error pin. This signal is synchronous to the device's internal oscillator.
crcerror_clk 1 Input CRC Error Verify IP core input clock signal.
crcerror_reset 1 Input CRC Error Verify IP core active-high logic reset signal.
emr[N-1:0] 46, 67, or 78 Output This data port contains the device's error message register contents, as defined in the device handbook SEU mitigation chapter:
  • Intel® Arria® 10 and Intel® Cyclone® 10 GX devices have 78-bit EMRs
  • Stratix® V, Arria® V, and Cyclone® V devices have 67-bit EMRs
  • Older devices have 46-bit EMRs
The EMR output signals comply with the Avalon® -ST interface definition.

N is 46, 67, or 78.

emr_valid 1 Output Active high when the emr signal contents are valid. This signal complies with the Avalon® interface definition.
emr_error 1 Output This signal is active high when the current EMR output transfer has an error and should be ignored. Typically, this signal indicates that the EMR input clock is too slow. This signal complies with the Avalon® interface definition.
endoffullchip 1 Output Optional output signal that indicates the end of each full-chip error detection cycle for the entire device. Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, Arria® V, and Cyclone® V devices only.
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