Error Message Register Unloader Intel FPGA IP Core User Guide

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ID 683866
Date 5/23/2018
Public
Document Table of Contents
Document Table of Contents x
1. Error Message Register Unloader Intel® FPGA IP Core User Guide
1. Error Message Register Unloader Intel® FPGA IP Core User Guide x
1.1. Features 1.2. IP Core Device Support 1.3. Resource Utilization and Performance 1.4. Functional Description 1.5. Parameter Settings 1.6. Installing and Licensing Intel® FPGA IP Cores 1.7. Customizing and Generating IP Cores 1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
1.4. Functional Description x
1.4.1. Error Message Register 1.4.2. Signals 1.4.3. Timing
1.4.3. Timing x
1.4.3.1. IP Timing Behavior ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices) 1.4.3.2. All Other Device Timing
1.7. Customizing and Generating IP Cores x
1.7.1. IP Catalog and Parameter Editor 1.7.2. The Parameter Editor 1.7.3. Specifying IP Core Parameters and Options 1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors)
1.7.3. Specifying IP Core Parameters and Options x
1.7.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors) x
1.7.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1. Error Message Register Unloader Intel® FPGA IP Core User Guide

1.4.3.2. All Other Device Timing

The following waveforms show the Error Message Register Unloader IP core timing behavior for Stratix® V, Stratix® IV, Arria® V, Arria® II GZ/GX, and Cyclone® V devices.
Figure 6. emr_read Timing Diagram
Figure 7. emr_valid Timing Diagram
Figure 8. Example EMR Errors Timing Diagram
  • In the case of 2 consecutive SEU errors, the IP core asserts emr_error for the lost EMR content.
  • The IP core asserts emr_error if it detects the falling edge of the crcerror pulse for the next error, before the IP core loads the previous content of the EMR user update register into the user shift register.
  • The rising edge of crcerror deasserts emr_error.
  • emr_error is a critical system state and can indicate that the Error Message Register Unloader input clock is too slow.
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