Error Message Register Unloader Intel FPGA IP Core User Guide

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ID 683866
Date 5/23/2018
Public
Document Table of Contents
Document Table of Contents x
1. Error Message Register Unloader Intel® FPGA IP Core User Guide
1. Error Message Register Unloader Intel® FPGA IP Core User Guide x
1.1. Features 1.2. IP Core Device Support 1.3. Resource Utilization and Performance 1.4. Functional Description 1.5. Parameter Settings 1.6. Installing and Licensing Intel® FPGA IP Cores 1.7. Customizing and Generating IP Cores 1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
1.4. Functional Description x
1.4.1. Error Message Register 1.4.2. Signals 1.4.3. Timing
1.4.3. Timing x
1.4.3.1. IP Timing Behavior ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices) 1.4.3.2. All Other Device Timing
1.7. Customizing and Generating IP Cores x
1.7.1. IP Catalog and Parameter Editor 1.7.2. The Parameter Editor 1.7.3. Specifying IP Core Parameters and Options 1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors)
1.7.3. Specifying IP Core Parameters and Options x
1.7.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors) x
1.7.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1. Error Message Register Unloader Intel® FPGA IP Core User Guide

1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide

Document Version Intel® Quartus® Prime Version Changes
2018.05.23 18.0
  • Renamed IP from Intel FPGA Error Message Register Unloader IP core to Error Message Register Unloader Intel FPGA IP core.
  • Updated figures emr_valid Signal for Correctable Errors after Power Up Only (Column-Based Type == 3'b0) and emr_valid Signal for Uncorrectable Errors.
Date Version Changes
December 2017 2017.12.18
  • Renamed the document as Intel FPGA Error Message Register Unloader IP Core User Guide.
  • Updated the "IP Core Device Support" table.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
July 2017 2017.07.15
  • Added Intel Cyclone 10 GX device support.
  • Changed V-Type to Column-Based Type in IP timing diagrams.
  • Provided separate parameterization instructions for Intel Quartus Prime Pro Edition and Intel Quartus Prime Standard Edition.
  • Updated for latest branding standards.
May 2016 2016.05.02
  • Removed feature bullet about Verilog HDL RTL support.
  • Changed Quartus II references to Quartus Prime.
June 2015 2015.06.12 Updated Arria 10 support details.
December 2014 2014.12.15 Initial release.
Level Two Title