AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

Download PDF
ID 683838
Date 10/12/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric x
1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA 1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA 1.3. Document Revision History for the AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer 1.2.4. Modifying Top Level File 1.2.5. Adding Pin Assignments for SPIM0 1.2.6. Hardware Programming File Compilation and Generation 1.2.7. Building U-Boot 1.2.8. Preparing QSPI Image 1.2.9. Building Linux 1.2.10. Building Yocto Rootfs 1.2.11. Building spidev Test Program 1.2.12. Creating SD Card Image 1.2.13. Booting the Board 1.2.14. Testing the SPIM0
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

1.2.8. Preparing QSPI Image

The following commands must be run inside an Intel® Quartus® Prime shell. Start the Intel® Quartus® Prime shell with the following command: 
~/intelFPGA_pro/20.3/embedded/embedded_command_shell.sh
cd ~/s10_spim_fpga
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof flash_image.jic \
   -o device=MT25QU128 \
   -o flash_loader=1SX280LU3 \
   -o hps_path=u-boot-socfpga/spl/u-boot-spl-dtb.hex \
   -o mode=ASX4
Level Two Title