AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

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ID 683838
Date 10/12/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric x
1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA 1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA 1.3. Document Revision History for the AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer 1.2.4. Modifying Top Level File 1.2.5. Adding Pin Assignments for SPIM0 1.2.6. Hardware Programming File Compilation and Generation 1.2.7. Building U-Boot 1.2.8. Preparing QSPI Image 1.2.9. Building Linux 1.2.10. Building Yocto Rootfs 1.2.11. Building spidev Test Program 1.2.12. Creating SD Card Image 1.2.13. Booting the Board 1.2.14. Testing the SPIM0
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

1.2.9. Building Linux

  1. Clone the Linux git tree and get the LTSI branch: 
    cd ~/ s10_spim_fpga/
git clone https://github.com/altera-opensource/linux-socfpga\
 linux-socfpga.a53
cd linux-socfpga.a53
git checkout -b test-kernel -t origin/socfpga-5.4.44-lts
make clean && make mrproper
  2. Change the kernel configuration by editing arch/arm64/configs/defconfig as follows: 
    CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_ALTERA=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
  3. Edit the device tree file: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts as follows:
    Add the FPGA clock that is used by the FPGA fabric: 
    clk_100: clk_100 {
   compatible = "fixed-clock";
   clock-frequency = <100000000>;	
   clock-output-names = "clk_100-out_clk";
};
    Add the PIO module which controls the SPI CS signal: 
    spi_cs_pio: gpio@0xf9010000 {
   compatible = "altr,pio-19.1", "altr,pio-1.0";
   reg = <0xf9010000 0x00000020>;
   clocks = <&clk_100>;
   altr,gpio-bank-width = <1>;	
   resetvalue = <1>;
   #gpio-cells = <2>;
   gpio-controller;
   status = "okay";
};
    Enable SPIM0, make it use the soft IP PIO as chip select, and enable it to be used by the spidev driver: 
    &spi0 {
   num-cs = <1>;
   cs-gpios = <&spi_cs_pio 0 0>;
   status = "okay";
   spidev@0 {
      compatible = "custom,spidev";
      reg = <0x0>;
      spi-max-frequency = <0x5F5E10>;
      enable-dma = <0x1>;
   };
};
  4. Edit the spidev driver source file: (drivers/spi/spidev.c) for the "compatible" property to match the created device tree entry. 
    { .compatible = "lineartechnology,ltc2488" },
 	{ .compatible = "ge,achc" },
 	{ .compatible = "semtech,sx1301" },
	{ .compatible = "custom,spidev" },
 	{},
  5. Build Linux kernel and device trees. 
    make clean && make mrproper
# enable JFFS2 and disable 4K sectors for booting from QSPI
echo "CONFIG_JFFS2_FS=y" >> arch/arm64/configs/defconfig
echo "CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n" >> arch/arm64/configs/defconfig
# reduce QSPI clock to work on early boards
sed -i 's/spi-max-frequency = <100000000>;/\
spi-max-frequency = <50000000>;/g'\
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
make defconfig
make -j 48 Image dtbs modules
make modules_install INSTALL_MOD_PATH=modules_install
rm -rf modules_install/lib/modules/*/build
rm -rf modules_install/lib/modules/*/source
cd ..
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