Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Intel® Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. Partial Reconfiguration Terminology 1.2. Partial Reconfiguration Process Sequence 1.3. Internal Host Partial Reconfiguration 1.4. External Host Partial Reconfiguration 1.5. Partial Reconfiguration Design Flow 1.6. Partial Reconfiguration Design Considerations 1.7. Hierarchical Partial Reconfiguration 1.8. Partial Reconfiguration Design Timing Analysis 1.9. Partial Reconfiguration Design Simulation 1.10. Partial Reconfiguration Design Debugging 1.11. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs) 1.12. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) 1.13. Avoiding PR Programming Errors 1.14. Exporting a Version-Compatible Compilation Database for PR Designs 1.15. Creating a Partial Reconfiguration Design Revision History
1.5. Partial Reconfiguration Design Flow x
1.5.1. Step 1: Identify Partial Reconfiguration Resources 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Floorplan the Design 1.5.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 1.5.5. Step 5: Define Personas 1.5.6. Step 6: Create Revisions for Personas 1.5.7. Step 7: Compile the Base Revision and Export the Static Region 1.5.8. Step 8: Setup PR Implementation Revisions 1.5.9. Step 9: Program the FPGA Device
1.5.3. Step 3: Floorplan the Design x
1.5.3.1. Applying Floorplan Constraints Incrementally
1.5.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
1.5.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 1.5.4.2. Adding the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP
1.5.9. Step 9: Program the FPGA Device x
1.5.9.1. Generating PR Bitstream Files 1.5.9.2. Partial Reconfiguration Bitstream Compatibility Checking 1.5.9.3. Raw Binary Programming File Byte Sequence Transmission Examples 1.5.9.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
1.6. Partial Reconfiguration Design Considerations x
1.6.1. Partial Reconfiguration Design Guidelines 1.6.2. PR Design Timing Closure Best Practices 1.6.3. PR File Management 1.6.4. Evaluating PR Region Initial Conditions 1.6.5. Creating Wrapper Logic for PR Regions 1.6.6. Creating Freeze Logic for PR Regions 1.6.7. Resetting the PR Region Registers 1.6.8. Promoting Global Signals in a PR Region 1.6.9. Planning Clocks and other Global Routing 1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents
1.6.3. PR File Management x
1.6.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona
1.6.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona x
1.6.3.1.1. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.6.8. Promoting Global Signals in a PR Region x
1.6.8.1. Viewing Row Clock Region Boundaries
1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents x
1.6.10.1. Clock Gating
1.7. Hierarchical Partial Reconfiguration x
1.7.1. Using Parent QDB Files from Different Compiles
1.8. Partial Reconfiguration Design Timing Analysis x
1.8.1. Running Timing Analysis on Aggregate Revisions
1.9. Partial Reconfiguration Design Simulation x
1.9.1. Partial Reconfiguration Simulation Flow
1.9.1. Partial Reconfiguration Simulation Flow x
1.9.1.1. Simulating PR Persona Replacement 1.9.1.2. altera_pr_persona_if Module 1.9.1.3. altera_pr_wrapper_mux_out Module 1.9.1.4. altera_pr_wrapper_mux_in Module
1.10. Partial Reconfiguration Design Debugging x
1.10.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.10.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
1.11. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs) x
1.11.1. PR Bitstream Security Validation ( Intel® Stratix® 10 Designs) 1.11.2. PR Bitstream Authentication ( Intel® Stratix® 10 Designs) 1.11.3. PR Bitstream Encryption ( Intel® Stratix® 10 Designs)
1.12. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) x
1.12.1. Generating an Encrypted PR Bitstream ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 1.12.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 1.12.3. Data Compression Comparison
1.14. Exporting a Version-Compatible Compilation Database for PR Designs x
1.14.1. Version-Compatible Database Flow for PR Designs 1.14.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller Intel® FPGA IP 2.3. Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP 2.4. Partial Reconfiguration External Configuration Controller Intel® FPGA IP 2.5. Partial Reconfiguration Region Controller Intel® FPGA IP 2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Intel® FPGA IP 2.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller Intel® FPGA IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications
2.3. Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller Intel® FPGA IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Configuring an External Host for Intel® Stratix® 10 or Intel® Agilex™ Designs
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Intel® FPGA IP x
2.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Intel® Quartus® Prime Pro Edition User Guides

1.8.1. Running Timing Analysis on Aggregate Revisions

To ensure timing closure of a design with multiple PR regions, you create aggregate revisions for all possible PR region combinations and run timing analysis.
  1. To open the Revisions dialog box, click Project > Revisions.
  2. To create a new revision, double-click <<new revision>>.
  3. Specify the Revision name and select the base revision for Based on Revision.
  4. To export the post-fit database from the base compile (static partition), type the following command in the Intel® Quartus® Prime shell: 
    quartus_cdb <project name> <base revision> --export_block \
     "root_partition" --snapshot final --file \
     "<base revision name>.qdb"
    Note: Ensure that you include all the .sdc and .ip files for the static and PR regions. To detect the clocks, ensure that the .sdc file for the PR Controller IP follows the entry of any .sdc file that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR Controller IP comes after any .ip or .sdc files that you use to create these clocks in the .qsf file for the project revision. Refer to Partial Reconfiguration Solutions IP User Guide for more information.
  5. To export the post-fit database from multiple personas (for the PR implementation revisions), type the following commands in the Intel® Quartus® Prime shell: 
    quartus_cdb <project name> -c <PR1 revision> --export_block \
     <PR1 Partition name> --snapshot final --file "pr1.qdb"
quartus_cdb <project name> -c <PR2 revision> --export_block \
     <PR2 Partition name> --snapshot final --file "pr2.qdb"
  6. To import the post-fit databases of the static region as an aggregate revision, type the following commands in the Intel® Quartus® Prime shell: 
    quartus_cdb <project name> -c <aggr_rev> --import_block \
     "root_partition" --file "<base revision name>.qdb"
quartus_cdb <project name> -c <aggr_rev> --import_block \
     <PR1 partition name> --file "pr1.qdb" 
quartus_cdb <project name> -c <aggr_rev> --import_block \
     <PR2 Partition name> --file "pr2.qdb"
  7. To integrate post-fit database of all the partitions, type the following command in the Intel® Quartus® Prime shell: 
    quartus_fit <project name> -c <aggr_rev>
    Note: The Fitter verifies the legality of the post-fit database, and combines the netlist for timing analysis. The Fitter does not reroute the design.
  8. To perform timing analysis on the aggregate revision, type the following command in the Intel® Quartus® Prime shell: 
    quartus_sta <proj name> -c <aggr_rev>
  9. Run timing analysis on aggregate revision for all possible PR persona combinations. If a specific persona fails timing closure, recompile the persona and perform timing analysis again.
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