Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration
ID
683834
Date
10/04/2021
Public
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1.1. Partial Reconfiguration Terminology
1.2. Partial Reconfiguration Process Sequence
1.3. Internal Host Partial Reconfiguration
1.4. External Host Partial Reconfiguration
1.5. Partial Reconfiguration Design Flow
1.6. Partial Reconfiguration Design Considerations
1.7. Hierarchical Partial Reconfiguration
1.8. Partial Reconfiguration Design Timing Analysis
1.9. Partial Reconfiguration Design Simulation
1.10. Partial Reconfiguration Design Debugging
1.11. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs)
1.12. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
1.13. Avoiding PR Programming Errors
1.14. Exporting a Version-Compatible Compilation Database for PR Designs
1.15. Creating a Partial Reconfiguration Design Revision History
1.5.1. Step 1: Identify Partial Reconfiguration Resources
1.5.2. Step 2: Create Design Partitions
1.5.3. Step 3: Floorplan the Design
1.5.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP
1.5.5. Step 5: Define Personas
1.5.6. Step 6: Create Revisions for Personas
1.5.7. Step 7: Compile the Base Revision and Export the Static Region
1.5.8. Step 8: Setup PR Implementation Revisions
1.5.9. Step 9: Program the FPGA Device
1.6.1. Partial Reconfiguration Design Guidelines
1.6.2. PR Design Timing Closure Best Practices
1.6.3. PR File Management
1.6.4. Evaluating PR Region Initial Conditions
1.6.5. Creating Wrapper Logic for PR Regions
1.6.6. Creating Freeze Logic for PR Regions
1.6.7. Resetting the PR Region Registers
1.6.8. Promoting Global Signals in a PR Region
1.6.9. Planning Clocks and other Global Routing
1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents
Verilog RTL for Clock Enable
VHDL RTL for Clock Enable
2.1. Internal and External PR Host Configurations
2.2. Partial Reconfiguration Controller Intel® FPGA IP
2.3. Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP
2.4. Partial Reconfiguration External Configuration Controller Intel® FPGA IP
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
2.8. Generating and Simulating Intel® FPGA IP
2.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive
2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.3.1. Agent Interface
2.3.2. Reconfiguration Sequence
2.3.3. Interrupt Interface
2.3.4. Parameters
2.3.5. Ports
2.3.6. Timing Specifications
2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
2.3.9. PR Control Block Signals
2.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
2.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
2.8.2. Running the Freeze Bridge Update script
2.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model
2.8.5. Generating the PR Persona Simulation Model
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1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents
Follow these guidelines to implement clock enable for on-chip memories with initialized contents:
- To avoid spurious writes during PR programming for memories with initialized contents, implement the clock enable circuit in the same PR region as the M20K or MLAB RAM. This circuit depends on an active-high clear signal from the static region.
- Before you begin the PR programming, assert this signal to disable the memory’s clock enable. Your system PR controller must deassert the clear signal on PR programming completion. You can use the freeze signal for this purpose.
- Use the Intel® Quartus® Prime IP Catalog or Platform Designer to instantiate the On-Chip Memory and RAM Intel® FPGA IP cores that include an option to automatically add this circuitry.
Figure 28. RAM Clock Enable Circuit for PR Region
Verilog RTL for Clock Enable
reg ce_reg; reg [1:0] ce_delay; always @(posedge clock, posedge freeze) begin if (freeze) begin ce_delay <= 2'b0; end else begin ce_delay <= {ce_delay[0], 1'b1}; end end always @(posedge clock, negedge ce_delay[1]) begin if (~ce_delay[1]) begin ce_reg <= 1'b0; end else begin ce_reg <= clken_in; end end wire ram_wrclocken; assign ram_wrclocken = ce_reg;
VHDL RTL for Clock Enable
ENTITY mem_enable_vhd IS PORT( clock : in std_logic; freeze : in std_logic; clken_in : in std_logic; ram_wrclocken : out std_logic); END mem_enable_vhd; ARCHITECTURE behave OF mem_enable_vhd is SIGNAL ce_reg: std_logic; SIGNAL ce_delay: std_logic_vector(1 downto 0); BEGIN PROCESS (clock, freeze) BEGIN IF ((clock'EVENT AND clock = '1') or (freeze'EVENT AND freeze = '1')) THEN IF (freeze = '1') THEN ce_delay <= "00"; ELSE ce_delay <= ce_delay(0) & '1'; END IF; END IF; END PROCESS; PROCESS (clock, ce_delay(1)) BEGIN IF ((clock'EVENT AND clock = '1') or (ce_delay(1)'EVENT AND ce_delay(1) = '0')) THEN IF (ce_delay(1) = '0') THEN ce_reg <= '0'; ELSE ce_reg <= clken_in; END IF; END IF; END PROCESS; ram_wrclocken <= ce_reg; END ARCHITECTURE behave;
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