Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 10/04/2021
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1.6.10. Implementing Clock Enable for On-Chip Memories with Initialized Contents

Follow these guidelines to implement clock enable for on-chip memories with initialized contents:
  1. To avoid spurious writes during PR programming for memories with initialized contents, implement the clock enable circuit in the same PR region as the M20K or MLAB RAM. This circuit depends on an active-high clear signal from the static region.
  2. Before you begin the PR programming, assert this signal to disable the memory’s clock enable. Your system PR controller must deassert the clear signal on PR programming completion. You can use the freeze signal for this purpose.
  3. Use the Intel® Quartus® Prime IP Catalog or Platform Designer to instantiate the On-Chip Memory and RAM Intel® FPGA IP cores that include an option to automatically add this circuitry.
Figure 28. RAM Clock Enable Circuit for PR Region

Verilog RTL for Clock Enable

reg ce_reg; reg [1:0] ce_delay; always @(posedge clock, posedge freeze) begin if (freeze) begin ce_delay <= 2'b0; end else begin ce_delay <= {ce_delay[0], 1'b1}; end end always @(posedge clock, negedge ce_delay[1]) begin if (~ce_delay[1]) begin ce_reg <= 1'b0; end else begin ce_reg <= clken_in; end end wire ram_wrclocken; assign ram_wrclocken = ce_reg;

VHDL RTL for Clock Enable

ENTITY mem_enable_vhd IS PORT( clock : in std_logic; freeze : in std_logic; clken_in : in std_logic; ram_wrclocken : out std_logic); END mem_enable_vhd; ARCHITECTURE behave OF mem_enable_vhd is SIGNAL ce_reg: std_logic; SIGNAL ce_delay: std_logic_vector(1 downto 0); BEGIN PROCESS (clock, freeze) BEGIN IF ((clock'EVENT AND clock = '1') or (freeze'EVENT AND freeze = '1')) THEN IF (freeze = '1') THEN ce_delay <= "00"; ELSE ce_delay <= ce_delay(0) & '1'; END IF; END IF; END PROCESS; PROCESS (clock, ce_delay(1)) BEGIN IF ((clock'EVENT AND clock = '1') or (ce_delay(1)'EVENT AND ce_delay(1) = '0')) THEN IF (ce_delay(1) = '0') THEN ce_reg <= '0'; ELSE ce_reg <= clken_in; END IF; END IF; END PROCESS; ram_wrclocken <= ce_reg; END ARCHITECTURE behave;