Stratix® 10 Variable Precision DSP Blocks User Guide

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ID 683832
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Variable Precision DSP Blocks Overview 2. Block Architecture Overview 3. Operational Mode Descriptions 4. Design Considerations 5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide 6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References 7. Multiply Adder IP Core References 8. ALTMULT_COMPLEX Intel® FPGA IP Core References 9. LPM_MULT Intel® FPGA IP Core References 10. Native Floating Point DSP Stratix® 10 FPGA IP References 11. LPM_DIVIDE (Divider) Intel FPGA IP Core 12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide
1. Stratix® 10 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Stratix® 10 Devices 1.3. Resources
2. Block Architecture Overview x
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic 2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic 2.3. Pre-adder for Fixed-Point Arithmetic 2.4. Internal Coefficient for Fixed-Point Arithmetic 2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic 2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic 2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic 2.8. Systolic Register for Fixed-Point Arithmetic 2.9. Double Accumulation Register for Fixed-Point Arithmetic 2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic 2.11. Exception Handling for Floating-Point Arithmetic
3. Operational Mode Descriptions x
3.1. Operational Modes for Fixed-Point Arithmetic 3.2. Operational Modes for Floating-Point Arithmetic
3.1. Operational Modes for Fixed-Point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. 18 × 19 Multiplication Summed with 36-Bit Input Mode 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.5. Systolic FIR Mode x
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-Point Arithmetic x
3.2.1. Single Floating-Point Arithmetic Functions 3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.1. Single Floating-Point Arithmetic Functions x
3.2.1.1. Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode
3.2.2. Multiple Floating-Point Arithmetic Functions x
3.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.2.2.2. Vector One Mode 3.2.2.3. Vector Two Mode 3.2.2.4. Direct Vector Dot Product 3.2.2.5. Complex Multiplication
4. Design Considerations x
4.1. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 4.2. Accumulator for Fixed-Point Arithmetic 4.3. Chainout Adder 4.4. Input Cascade for Fixed-Point Arithmetic 4.5. DSP Block Cascade Limit in Agilex™ 7 Devices
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide x
5.1. 'X' Propagation Support in Simulation
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References x
6.1. Native Fixed Point DSP Stratix® 10 FPGA IP Release Information 6.2. Supported Operational Modes 6.3. Maximum Input Data Width for Fixed-Point Arithmetic 6.4. Parameterizing Native Fixed Point DSP IP Core 6.5. Signals
6.3. Maximum Input Data Width for Fixed-Point Arithmetic x
6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
6.4. Parameterizing Native Fixed Point DSP IP Core x
6.4.1. Native Fixed Point DSP Stratix® 10 FPGA IP Parameters
7. Multiply Adder IP Core References x
7.1. Multiply Adder Intel FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
7.2. Features x
7.2.1. Pre-adder 7.2.2. Systolic Delay Register 7.2.3. Pre-load Constant 7.2.4. Double Accumulator
7.2.1. Pre-adder x
7.2.1.1. Pre-adder Simple Mode 7.2.1.2. Pre-adder Coefficient Mode 7.2.1.3. Pre-adder Input Mode 7.2.1.4. Pre-adder Square Mode 7.2.1.5. Pre-adder Constant Mode
7.3. Parameters x
7.3.1. General Tab 7.3.2. Extra Modes 7.3.3. Multipliers Tab 7.3.4. Preadder Tab 7.3.5. Accumulator Tab 7.3.6. Systolic/Chainout Tab 7.3.7. Pipelining Tab
8. ALTMULT_COMPLEX Intel® FPGA IP Core References x
8.1. ALTMULT_COMPLEX Intel FPGA IP Release Information 8.2. Features 8.3. Complex Multiplication 8.4. Parameters 8.5. Signals
9. LPM_MULT Intel® FPGA IP Core References x
9.1. LPM_MULT Intel FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
9.3. Parameters x
9.3.1. General Tab 9.3.2. General 2 Tab 9.3.3. Pipelining Tab
10. Native Floating Point DSP Stratix® 10 FPGA IP References x
10.1. Native Floating Point DSP Stratix® 10 FPGA IP Release Information 10.2. Native Floating Point DSP Stratix® 10 FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP 10.4. Native Floating Point DSP Stratix® 10 FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP x
10.3.1. Native Floating Point DSP Stratix® 10 FPGA IP Parameters
11. LPM_DIVIDE (Divider) Intel FPGA IP Core x
11.1. LPM_DIVIDE Intel® FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters x
11.7.1. General Tab 11.7.2. General1 Tab
1. Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core References
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide

7.3.2. Extra Modes

Table 37.  Extra Modes Tab
Parameter Value Default Value Description
Outputs Configuration
Register output of the adder unit

On

Off

 Off

Turn on this option to enable output register of the adder module.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the clock source for output registers.

You must select Register output of the adder unit to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Adder Operation
What operation should be performed on outputs of the first pair of multipliers?

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the first and second multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select more than two multipliers to enable this parameter.

Register 'addnsub1' input

On

Off

 Off Turn on this option to enable input register for addnsub1 port.

You must select VARIABLE for What operation should be performed on outputs of the first pair of multipliers to enable this parameter.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What operation should be performed on outputs of the second pair of multipliers?

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the third and fourth multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select the value 4 for What is the number of multipliers? to enable this parameter.

Register 'addnsub3' input

On

Off

 Off Turn on this option to enable input register for addnsub3 signal.

You must select VARIABLE for What operation should be performed on outputs of the second pair of multipliers to enable this parameter.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Polarity
Enable ‘use_subadd’

On

Off

 Off

Turn on this option to reverse the function of addnsub input port.

When this option is turned on, do the following:
  • drive addnsub to high for subtraction operation
  • drive addnsub to low for addition operation
Level Two Title