Stratix® 10 Variable Precision DSP Blocks User Guide

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ID 683832
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Variable Precision DSP Blocks Overview 2. Block Architecture Overview 3. Operational Mode Descriptions 4. Design Considerations 5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide 6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References 7. Multiply Adder IP Core References 8. ALTMULT_COMPLEX Intel® FPGA IP Core References 9. LPM_MULT Intel® FPGA IP Core References 10. Native Floating Point DSP Stratix® 10 FPGA IP References 11. LPM_DIVIDE (Divider) Intel FPGA IP Core 12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide
1. Stratix® 10 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Stratix® 10 Devices 1.3. Resources
2. Block Architecture Overview x
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic 2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic 2.3. Pre-adder for Fixed-Point Arithmetic 2.4. Internal Coefficient for Fixed-Point Arithmetic 2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic 2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic 2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic 2.8. Systolic Register for Fixed-Point Arithmetic 2.9. Double Accumulation Register for Fixed-Point Arithmetic 2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic 2.11. Exception Handling for Floating-Point Arithmetic
3. Operational Mode Descriptions x
3.1. Operational Modes for Fixed-Point Arithmetic 3.2. Operational Modes for Floating-Point Arithmetic
3.1. Operational Modes for Fixed-Point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. 18 × 19 Multiplication Summed with 36-Bit Input Mode 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.5. Systolic FIR Mode x
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-Point Arithmetic x
3.2.1. Single Floating-Point Arithmetic Functions 3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.1. Single Floating-Point Arithmetic Functions x
3.2.1.1. Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode
3.2.2. Multiple Floating-Point Arithmetic Functions x
3.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.2.2.2. Vector One Mode 3.2.2.3. Vector Two Mode 3.2.2.4. Direct Vector Dot Product 3.2.2.5. Complex Multiplication
4. Design Considerations x
4.1. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 4.2. Accumulator for Fixed-Point Arithmetic 4.3. Chainout Adder 4.4. Input Cascade for Fixed-Point Arithmetic 4.5. DSP Block Cascade Limit in Agilex™ 7 Devices
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide x
5.1. 'X' Propagation Support in Simulation
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References x
6.1. Native Fixed Point DSP Stratix® 10 FPGA IP Release Information 6.2. Supported Operational Modes 6.3. Maximum Input Data Width for Fixed-Point Arithmetic 6.4. Parameterizing Native Fixed Point DSP IP Core 6.5. Signals
6.3. Maximum Input Data Width for Fixed-Point Arithmetic x
6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
6.4. Parameterizing Native Fixed Point DSP IP Core x
6.4.1. Native Fixed Point DSP Stratix® 10 FPGA IP Parameters
7. Multiply Adder IP Core References x
7.1. Multiply Adder Intel FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
7.2. Features x
7.2.1. Pre-adder 7.2.2. Systolic Delay Register 7.2.3. Pre-load Constant 7.2.4. Double Accumulator
7.2.1. Pre-adder x
7.2.1.1. Pre-adder Simple Mode 7.2.1.2. Pre-adder Coefficient Mode 7.2.1.3. Pre-adder Input Mode 7.2.1.4. Pre-adder Square Mode 7.2.1.5. Pre-adder Constant Mode
7.3. Parameters x
7.3.1. General Tab 7.3.2. Extra Modes 7.3.3. Multipliers Tab 7.3.4. Preadder Tab 7.3.5. Accumulator Tab 7.3.6. Systolic/Chainout Tab 7.3.7. Pipelining Tab
8. ALTMULT_COMPLEX Intel® FPGA IP Core References x
8.1. ALTMULT_COMPLEX Intel FPGA IP Release Information 8.2. Features 8.3. Complex Multiplication 8.4. Parameters 8.5. Signals
9. LPM_MULT Intel® FPGA IP Core References x
9.1. LPM_MULT Intel FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
9.3. Parameters x
9.3.1. General Tab 9.3.2. General 2 Tab 9.3.3. Pipelining Tab
10. Native Floating Point DSP Stratix® 10 FPGA IP References x
10.1. Native Floating Point DSP Stratix® 10 FPGA IP Release Information 10.2. Native Floating Point DSP Stratix® 10 FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP 10.4. Native Floating Point DSP Stratix® 10 FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP x
10.3.1. Native Floating Point DSP Stratix® 10 FPGA IP Parameters
11. LPM_DIVIDE (Divider) Intel FPGA IP Core x
11.1. LPM_DIVIDE Intel® FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters x
11.7.1. General Tab 11.7.2. General1 Tab
1. Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core References
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide

6.5. Signals

The following figure shows the input and output signals of the Native Fixed Point DSP Stratix® 10 FPGA IP core.

Figure 31.  Native Fixed Point DSP Stratix® 10 FPGA IP Core Signals
Table 28.  Data Input SignalsThe simulation model for this IP supports undetermined input value (X) to the following signals. When you provide X value to these signals, the X value is propagated on the output signals.
Signal Name Type Width Description
ax[26:0] Input 27 Input data bus to top multiplier.

This signal is not available when internal coefficient feature is enabled.

ay[26:0] Input 27 Input data bus to top multiplier.

When pre-adder is enabled, these signals are served as input to the top pre-adder.

az[25:0] Input 26

These signal are input to the top pre-adder.

These signals are only available when pre-adder is enabled and not available in m18x18_plus36 operational mode.

bx[17:0] Input 18 Input data bus to bottom multiplier.

These signals are not available in m27×27operational mode and when internal coefficient feature is enabled.

by[18:0] Input 19 Input data bus to bottom multiplier.

When pre-adder is enabled, these signals serve as input signals to the bottom pre-adder.

These signals are not available in m27×27 operational mode.

bz[17:0] Input 18

These signals are input signals to the bottom pre-adder.

These signals are only available when pre-adder is enabled.

These signals are not available in m18x18_plus36 and m27×27 operational modes.

Table 29.  Data Output SignalsThe simulation model for this IP supports undetermined output value (X) for the following signals. When you provide X value as the input, the X value is propagated on the output signals.
Signal Name Type Width Description
resulta[63:0] Output 64 Output data bus from top multiplier.

Only in m18×18_full mode, these signals support up to 37 bits.

resultb[36:0] Output 37 Output data bus from bottom multiplier.

These signals are only available in m18×18_full operational mode.

Table 30.  Clock, Enable and Clear SignalsThe simulation model for this IP supports undetermined input value (X) to the following signals. When you provide X values to these signals, the X value is propagated on the output signals.
Signal Name Type Width Description
clk[2:0] Input 3 Input clock for all registers.

These clock are only available if any of the input registers, pipeline registers or output register is set to Clock0 or Clock1 or Clock2.

  • clk[0] = Clock0
  • clk[1] = Clock1
  • clk[2] = Clock2
ena[2:0] Input 3 Clock enable for clk[2:0].

These signals are active-High.

  • ena[0] is for Clock0
  • ena[1] is for Clock1
  • ena[2] is for Clock2
clr[1:0] Input 2 These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of CLEAR signal parameter.

These signals are active-High.

Use clr[0] for all input registers and use clr[1] for all pipeline and output registers.

By default, this signal is de-asserted.

Table 31.  Dynamic Control SignalsFor summary of supported dynamic control features for each operational modes, please refer to Table 2. The simulation model for this IP supports undetermined input value (X) to the following signals. When you provide X value to these signals, the X value is propagated on the output signals.
Signal Name Type Width Description
sub Input 1 Dynamic input signal to control the operation of the adder module.
  • De-assert this signal to add the output of the top multiplier with the output of the bottom multiplier.
  • Assert this signal to subtract the output of the top multiplier from the output of the bottom multiplier.

By default, this signal is de-asserted. You can assert or de-assert this signal during run-time.

This signal is not available in m18x18_full, m18x18_full_top, and m27x27 operational modes.

negate Input 1 Dynamic input signal to control the operation of the chainout adder module.
  • Deassert this signal to add the sum of the top and bottom multipliers with the chainin data input bus and accumulate loopback data.
  • Assert this signal to subtract the sum of the top and bottom multipliers from the chainin data input bus and accumulate loopback data.

By default, this signal is de-asserted. You can assert or de-assert this signal during run-time.

This signal is not available in m18x18_full and m18x18_full_topoperational modes.

accumulate Input 1 Input signal to enable or disable the accumulator feature.
  • De-assert this signal to generate the current result without accumulating the previous result.
  • Assert this signal to add the current result to the previous result.

By default, this signal is de-asserted. You can assert or de-assert this signal during run-time.

This signal is not available in m18x18_full and m18x18_full_topoperational modes.

loadconst Input 1 Input signal to enable or disable the load constant feature.
  • De-assert this signal to disable the load constant feature.
  • Assert this signal to add a preload constant to the result to perform a biased rounding.

By default, this signal is de-asserted. You can assert or de-assert this signal during run-time.

This signal is not available in m18x18_full and m18x18_full_top operational modes.

Table 32.  Internal Coefficient PortsFor summary of supported features for each operational modes, please refer to Table 1. The simulation model for this IP supports undetermined input value (X) to the following signals. When you provide X value to these signals, the X value is propagated on the output signals.
Signal Name Type Width Description
coefsela[2:0] Input 3 Input selection signals for 8 coefficient values defined by user for the top multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_a_0 to coef_a_7.
  • coefsela[2:0] = 000 refers to coef_a_0
  • coefsela[2:0] = 001 refers to coef_a_1
  • coelsela[2:0] = 010 refers to coef_a_2 and so forth.

These signals are only available when the internal coefficient feature is enabled.

These signals are not available in m18x18_plus36 operational mode.

coefselb[2:0] Input 3 Input selection signals for 8 coefficient values defined by user for the bottom multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_b_0 to coef_b_7.
  • coefselb[2:0] = 000 refers to coef_b_0
  • coefselb[2:0] = 001 refers to coef_b_1
  • coelselb[2:0] = 010 refers to coef_b_2 and so forth.

These signals are only available when the internal coefficient feature is enabled.

These signals are not available in m18x18_full, m18x18_plus36 and m27x27 operational modes.

Table 33.  Input Cascade Signals
Signal Name Type Width Description
scanin[26:0] Input 27 Input data bus for input cascade module.

Connect these signals to the scanout signals from the preceding DSP core.

scanout[26:0] Output 27 Output data bus of the input cascade module.

Connect these signals to the scanin signals of the next DSP core.

Table 34.  Output Cascade Signals
Signal Name Type Width Description
chainin[63:0] Input 64 Input data bus for output cascade module.

Connect these signals to the chainout signals from the preceding DSP core.

In 18 x 18 systolic mode, only 44 bits of output cascade is supported.

chainout[63:0] Output 64 Output data bus of the output cascade module.

Connect these signals to the chainin signals of the next DSP core.

In 18 x 18 systolic mode, only 44 bits of output cascade is supported.

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