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1. Intel® Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Intel® Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core Reference
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Intel® Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Intel® Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Intel® Stratix® 10 Variable Precision DSP Blocks User Guide
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic
2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic
2.3. Pre-adder for Fixed-Point Arithmetic
2.4. Internal Coefficient for Fixed-Point Arithmetic
2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic
2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic
2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic
2.8. Systolic Register for Fixed-Point Arithmetic
2.9. Double Accumulation Register for Fixed-Point Arithmetic
2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic
2.11. Exception Handling for Floating-Point Arithmetic
10.1. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Release Information
10.2. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Supported Operational Modes
10.3. Parameterizing the Native Floating Point DSP Intel® Stratix® 10 FPGA IP
10.4. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Signals
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2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic
In addition to the input and output registers, there are 2 columns of pipeline registers for fixed-point arithmetic. Pipeline registers are used to get the maximum Fmax performance. The pipeline registers can be bypassed if high Fmax is not needed.
The following variable precision DSP block signals control the pipeline registers within the variable precision DSP block:
- CLK[2..0]
- ENA[2..0]
- CLR[1]
Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all latency layers of the pipeline registers or use any one, two or three layers of pipeline registers.