OpenCL* on Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Quick Start User Guide

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ID 683831
Date 6/05/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Setting Up the Host Machine 3. Running Diagnostics 4. OpenCL* Support for Multi-Card Systems 5. Running Samples 6. Compiling OpenCL* Kernels 7. Intel® PAC with Intel® Arria® 10 GX FPGA Security for OpenCL* Applications 8. OpenCL* on the Intel® PAC with Intel® Arria® 10 GX FPGA Quick Start User Guide Archives 9. Document Revision History for OpenCL* Quick Start User Guide Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary 1.3. Acronyms
2. Setting Up the Host Machine x
2.1. Introduction 2.2. Initializing the Environment for OpenCL* with Intel Acceleration Stack 2.3. Initializing the Intel® Acceleration Stack for OpenCL* in a Virtualized Environment
2.1. Introduction x
2.1.1. Release Content
5. Running Samples x
5.1. Running Hello World 5.2. Running Vector Add
6. Compiling OpenCL* Kernels x
6.1. Checking Timing Results
1. About this Document
2. Setting Up the Host Machine
3. Running Diagnostics
4. OpenCL* Support for Multi-Card Systems
5. Running Samples
6. Compiling OpenCL* Kernels
7. Intel® PAC with Intel® Arria® 10 GX FPGA Security for OpenCL* Applications
8. OpenCL* on the Intel® PAC with Intel® Arria® 10 GX FPGA Quick Start User Guide Archives
9. Document Revision History for OpenCL* Quick Start User Guide Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

1.3. Acronyms

Table 3.  Acronyms

Acronyms

 Expansion

Description

AFU

Accelerator Functional Unit

Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.

AF

Accelerator Function

Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.

API

 Application Programming Interface

A set of subroutine definitions, protocols, and tools for building software applications.

FIM

FPGA Interface Manager

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The Accelerator Function (AF) interfaces with the FIM at run time.

OPAE

Open Programmable Acceleration Engine

The OPAE is a software framework for managing and accessing AFs. 

RoT Root of Trust A source that can be trusted, such as the BMC in the Intel® PAC.
BSP Board Support Package A typical Intel® PAC BSP consists of software layers and a hardware project created using the Intel® Quartus® Prime Pro Edition software that Intel® FPGA SDK for OpenCL* compiler stitches accelerator code into and compiles. The BSP resides in the AFU.
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