Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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3.5.3. Configuration Access Mechanism

Table 26.  Configuration Access Mechanism in 29-bit and 14-bit addressing
Access 29-bit Address 14-bit Address
EP Config Space Write Single Write: AVMM write to EP Register address (AVMM address includes BDF+ Register) with actual data Two Writes:
  • Write BDF info to 0x0004 (with 13th bit set to 1)
  • AVMM Write to EP Register address (with 13th bit set to 0) with actual data
EP Config Space Read
  • AVMM read to EP Register address (AVMM address includes BDF+Register)
  • Type1/Type0 based on 28th bit
  • CplD data is available on AVMM read data bus
  • One AVMM write of BDF info to 0x0004 (with 13th bit set to 1)
  • One AVMM read to EP Register address (with 13th bit set to 0)
  • Type1/Type0 based on 12th bit
  • CplD data is available on AVMM read data bus
Figure 16. Config Write Type 0 with 14-bit Address Format
Figure 17. Config Read Type 0 with 14-bit Address Format