Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.10. Config TL Interface

Table 49.  Config TL Interface Signals
Signal Name I/O Type Description

H-Tile: usr_hip_tl_config_func_o [1:0]

P-Tile and F-Tile: usr_hip_tl_config_func_o [2:0]

Output Specifies the function whose Configuration Space register values are being driven out on tl_cfg_ctl_o bus.

H-Tile: usr_hip_tl_config_add_o[3:0]

P-Tile and F-Tile: usr_hip_tl_config_add_o[4:0]

Output

This address bus contains the index indicating which Configuration Space register information is being driven onto the tl_cfg_ctl_o bus.

For detailed information for Config Space registers, refer to the Configuration Output Interface of the P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide or Configuration Output Interface of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide

H-Tile: usr_hip_tl_config_ctl_o[31:0]

P-Tile and F-Tile: usr_hip_tl_config_ctl_o[15:0]

Output

Multiplexed data output from the register specified by tl_cfg_add_o[4:0].

For detailed information for Config Space registers, refer to Configuration Output Interface of the P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide or Configuration Output Interface of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide