Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021
Public

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Document Table of Contents

5.1.2. MCDMA Settings

Figure 16. MCDMA Settings Parameters
Table 40.  MCDMA Settings
Parameter Value Description
Enable PIPE PHY Interface On/Off

PIPE PHY Interface is for simulation only. This should be enabled for example design generation. Default: On

PIO BAR2 Address Width

NA

128 Bytes - 7 bits ~ 8 EBytes - 63 bits

Address width for PIO AVMM port. Default address width is 22 bits

User Mode

Multi channel DMA

Bursting Master

Bursting Slave

BAM+BAS

BAM+MCDMA

This option allows user to configure the mode of operation for MCDMA IP. MCDMA mode has the DMA functionality. BAM and BAS offer Bursting Master and Slave AVMM capabilities without DMA functionality

Interface type

AVMM

AVST

User logic interface type for D2HDM and H2DDM.

Default: Avalon-MM Interface

Number of ports

1

4

For AVMM Interface type, this is fixed to 1. For AVST interface type, you can select either 1 or 4 ports.

Enable User-MSIX

On / Off

User MSI-X enables user application to initiate interrupts through MCDMA, this option is available only if the user selects MCDMA mode

Enable User-FLR

On / Off

User FLR interface allows passing of FLR signals to the user side application

D2H Prefetch channels

8

16

32

64

128

256

Sets the D2H Prefetch channels.

Applicable to AVST 1 port interface only.

Maximum Descriptor Fetch

16

32

64

Sets the maximum descriptors that are fetched per D2H prefetch channel.

Applicable to AVST 1 port interface only.

Enable Metadata

On / Off

Enable Metadata.

Applicable to AVST 1 port interface only.

Enable config slave

On / Off

This parameter is not user configurable. This is turned on automatically when a Root Port mode is selected. Not applicable to Endpoint mode.