EPCQ-A Serial Configuration Device Datasheet

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ID 683818
Date 10/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. EPCQ-A Serial Configuration Device Datasheet
1. EPCQ-A Serial Configuration Device Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Pin Information 1.5. Device Package and Ordering Code 1.6. Memory Array Organization 1.7. Memory Operations 1.8. Status Register 1.9. Summary of Operation Codes 1.10. Power Mode 1.11. Timing Information 1.12. Programming and Configuration File Support 1.13. Appendix: SFDP Register Definitions 1.14. Document Revision History for the EPCQ-A Serial Configuration Device Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. AC Measurement Conditions 1.3.5. ICC Supply Current 1.3.6. Capacitance
1.4. Pin Information x
1.4.1. Pin-Out Diagram for EPCQ4A, EPCQ16A and EPCQ32A Devices 1.4.2. Pin-Out Diagram for EPCQ64A and EPCQ128A Devices 1.4.3. EPCQ-A Device Pin Description
1.5. Device Package and Ordering Code x
1.5.1. Package 1.5.2. Ordering Code
1.6. Memory Array Organization x
1.6.1. Address Range for EPCQ4A 1.6.2. Address Range for EPCQ16A 1.6.3. Address Range for EPCQ32A 1.6.4. Address Range for EPCQ64A 1.6.5. Address Range for EPCQ128A
1.7. Memory Operations x
1.7.1. Timing Requirements
1.8. Status Register x
1.8.1. Read Status Operation 1.8.2. Write Status Operation
1.9. Summary of Operation Codes x
1.9.1. Read Bytes Operation (03h) 1.9.2. Fast Read Operation (0Bh) 1.9.3. Extended Dual Input Fast Read Operation (BBh) 1.9.4. Extended Quad Input Fast Read Operation (EBh) 1.9.5. Read Device Identification Operation (9Fh) 1.9.6. Read Silicon Identification Operation (ABh) 1.9.7. Write Enable Operation (06h) 1.9.8. Write Disable Operation (04h) 1.9.9. Write Bytes Operation (02h) 1.9.10. Quad Input Fast Write Bytes Operation (32h) 1.9.11. Erase Bulk Operation (C7h) 1.9.12. Erase Sector Operation (D8h) 1.9.13. Erase Subsector Operation (20h) 1.9.14. Read SFDP Register Operation (5Ah)
1.11. Timing Information x
1.11.1. Write Operation Timing 1.11.2. Read Operation Timing
1. EPCQ-A Serial Configuration Device Datasheet

1.7.1. Timing Requirements

When the active low chip select (nCS) signal is driven low, shift in the operation code into the EPCQ-A device using theDATA0 pin. Each operation code bit is latched into the EPCQ-A device at rising edges of the DCLK signal.

While executing an operation, shift in the desired operation code, followed by the address or data bytes. See related information for more information about the address and data bytes. The device must drive the nCS pin high after the last bit of the operation sequence is shifted in.

For read operations, the data read is shifted out on the DATA[3:0] pins. You can drive the nCS pin high when any bit of the data is shifted out.

For write and erase operations, drive the nCS pin high at a byte boundary, that is in a multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.

All attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected.

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