EPCQ-A Serial Configuration Device Datasheet

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ID 683818
Date 10/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. EPCQ-A Serial Configuration Device Datasheet
1. EPCQ-A Serial Configuration Device Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Pin Information 1.5. Device Package and Ordering Code 1.6. Memory Array Organization 1.7. Memory Operations 1.8. Status Register 1.9. Summary of Operation Codes 1.10. Power Mode 1.11. Timing Information 1.12. Programming and Configuration File Support 1.13. Appendix: SFDP Register Definitions 1.14. Document Revision History for the EPCQ-A Serial Configuration Device Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. AC Measurement Conditions 1.3.5. ICC Supply Current 1.3.6. Capacitance
1.4. Pin Information x
1.4.1. Pin-Out Diagram for EPCQ4A, EPCQ16A and EPCQ32A Devices 1.4.2. Pin-Out Diagram for EPCQ64A and EPCQ128A Devices 1.4.3. EPCQ-A Device Pin Description
1.5. Device Package and Ordering Code x
1.5.1. Package 1.5.2. Ordering Code
1.6. Memory Array Organization x
1.6.1. Address Range for EPCQ4A 1.6.2. Address Range for EPCQ16A 1.6.3. Address Range for EPCQ32A 1.6.4. Address Range for EPCQ64A 1.6.5. Address Range for EPCQ128A
1.7. Memory Operations x
1.7.1. Timing Requirements
1.8. Status Register x
1.8.1. Read Status Operation 1.8.2. Write Status Operation
1.9. Summary of Operation Codes x
1.9.1. Read Bytes Operation (03h) 1.9.2. Fast Read Operation (0Bh) 1.9.3. Extended Dual Input Fast Read Operation (BBh) 1.9.4. Extended Quad Input Fast Read Operation (EBh) 1.9.5. Read Device Identification Operation (9Fh) 1.9.6. Read Silicon Identification Operation (ABh) 1.9.7. Write Enable Operation (06h) 1.9.8. Write Disable Operation (04h) 1.9.9. Write Bytes Operation (02h) 1.9.10. Quad Input Fast Write Bytes Operation (32h) 1.9.11. Erase Bulk Operation (C7h) 1.9.12. Erase Sector Operation (D8h) 1.9.13. Erase Subsector Operation (20h) 1.9.14. Read SFDP Register Operation (5Ah)
1.11. Timing Information x
1.11.1. Write Operation Timing 1.11.2. Read Operation Timing
1. EPCQ-A Serial Configuration Device Datasheet

1.4.3. EPCQ-A Device Pin Description

Table 8.  EPCQ-A Device Pin Description
Pin Name AS x1 Pin-Out Diagram AS x4 Pin-Out Diagram Pin Type Description
Pin Number in 8-Pin SOIC Package Pin Number in 16-Pin SOIC Package Pin Number in 8-Pin SOIC Package Pin Number in 16-Pin SOIC Package
DATA0 5 15 5 15 I/O For AS x1 mode, use this pin as an input signal pin to write or program the EPCQ-A device. During write or program operations, data are latched at rising edges of the DCLK signal. This pin is equivalent to the ASDI pin in EPCS devices.

For AS x4 mode, use this pin as an I/O signal pin. During write or program operations, this pin acts as an input pin that serially transfers data into the EPCQ-A device. The data are latched at rising edges of the DCLK signal. During read or configuration operations, this pin acts as an output signal pin that serially transfers data out of the EPCQ-A device to the FPGA. The data is shifted out at falling edges of the DCLK signal.

During the quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ-A device. The data is latched at rising edges of the DCLK signal. During extended dual input fast read or extended quad input fast read operations, this pin acts as an output signal pin that serially transfers data out of the EPCQ-A device to the FPGA. The data is shifted out at falling edges of the DCLK signal.

DATA1 2 8 2 8 I/O For AS x1 and x4 modes, use this pin as an output signal pin that serially transfers data out of the EPCQ-A device to the FPGA during read or configuration operations. The transition of the signal is at falling edges of the DCLK signal. This pin is equivalent to the DATA pin in EPCS devices.

During the quad input fast write bytes operation, this pin acts as an input signal pin that serially transfers data into the EPCQ-A device. The data is latched at rising edges of the DCLK signal.

During extended quad input fast read operations, this pin acts as an output signal pin that serially transfer data out of the EPCQ-A device to the FPGA. The data is shifted out at falling edges of the DCLK signal. During read, configuration, or program operations, you can enable the EPCQ-A device by pulling the nCS signal low.

DATA2 — — 3 9 I/O For AS x1 mode, this pin must connect to VCC.

For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ-A device to the FPGA during read or configuration operations. The transition of the signal is at falling edges of the DCLK signal.

During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ-A device to the FPGA. The data is shifted out at falling edges of the DCLK signal.

DATA3 — — 7 1 I/O For AS x1 mode, this pin must connect to VCC.

For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ-A device to the FPGA during read or configuration operations. The transition of the signal is at falling edges of the DCLK signal.

During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ-A device to the FPGA. The data is shifted out at falling edges of the DCLK signal.

nCS 1 7 1 7 Input The active low nCS input signal toggles at the beginning and end of a valid operation. When this signal is high, the device is deselected and the DATA[3:0] pins are tri-stated. When this signal is low, the device is enabled and is in active mode. After power up, the EPCQ-A device requires a falling edge on the nCS signal before you begin any operation.
DCLK 6 16 6 16 Input The FPGA provides the DCLK signal. This signal provides the timing for the serial interface. The data presented on the DATA[3:0] pins are latched to the EPCQ-A device at rising edges of the DCLK signal. The data on the DATA[3:0] pins change after the falling edge of the DCLK signal and are latched in to the FPGA on the next falling edge of the DCLK signal.
nRESET — 3 — 3 Input Dedicated hardware reset pin. When it’s driven low for a minimum period of ~1μS, the EPCQ-A device will terminate any external or internal operations and return to its power-on state.

There is an internal pull-up resistor for the dedicated nRESET pin on the SOIC-16 package. If the reset function is not needed, you can connect it to VCC or leave it unconnected.

VCC 8 2 8 2 Power Connect the power pins to a 3.3-V power supply.
GND 4 10 4 10 Ground Ground pin.
Level Two Title