F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/11/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel FPGA Hard IP Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Testing the Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel FPGA Hard IP Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.3. Simulation

The testbench provides basic functionality such as the startup and wait for lock and send and receive a few packets utilizing the PTP feature.
Since Fast Sim model does not support the PTP timestamp accuracy, the model is not enabled by default in the designs with enabled PTP feature. To utilize the Fast Sim model for functional purpose simulation, refer to Fast Sim Model for FGT Variants.
Note: In PTP design examples, the simulation printout displays the timestamp accuracy as RX ITS - TX ETS information.
  1. Assert global reset (i_rst_n) to reset the F-Tile Ethernet Intel FPGA Hard IP.
  2. Wait until resets acknowledgment. The o_rst_ack_n signal goes low.
  3. Deasserts the global reset.
  4. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  5. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  6. Perform the PTP user flow until tx_ptp_ready and rx_ptp_ready signals are set to 1.
  7. Write to PTP Asymmetry Delay and peer-to-peer MeanPathDelay Avalon® memory-mapped interface registers.
  8. Reset the PTP monitor.
  9. Read TX packet data information from 0x00 - 0x34 registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the TX packet statistics.
    • 0x020/0x24: TX start of packet counter (LSB/MSB)
    • 0x28/0x2C: TX end of packet counter (LSB/MSB)
    • 0x30/0x34: TX error counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  10. Read RX packet data information from 0x38 - 0x4C registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the RX packet statistics.
    • 0x38/0x3C: RX start of packet counter (LSB/MSB)
    • 0x40/0x44: RX end of packet counter (LSB/MSB)
    • 0x48/0x4C: RX error counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  11. Compare read counters to ensure 16 packets were sent and received.
  12. Instruct packet client to stop data transmission and clear the counters by writing hw_pc_ctrl[2:0]=3'b100 to stop the packet generator.
  13. Start the PTP checker.
    1. Wait until the packet transmission is complete. Poll the TX_PKT_VALID bit to monitor the transmission status.
    2. Read TX packet data information from 0x102 - 0x104 registers in sequential order, starting from the 0x102 register. The PTP monitor logic refreshes the 0x102 - 0x104 registers content to next data when read from 0x104 register.
    3. Repeat the previous step until the TX_PKT_EOP bit is set to 1 indicating the read operation reached the end of the packet.
    4. Read TX PTP command information from 0x105 - 0x10A registers in sequential order, starting from the 0x105 register. The PTP monitor logic refreshes the 0x105 - 0x10A registers content to next data when read from 0x10A register.
    5. If TX PTP command indicates a PTP packet:
      1. Wait until the TX egress timestamp is available. Use the TX_PTP_ETS_VALID signal to monitor the status.
      2. Read the TX egress timestamp from the 0x10C - 0x10F registers in sequential order, starting with the 0x10C register.
      The PTP monitor logic refreshes content of 0x10C - 0x10F registers to next data when read from the 0x10F register.
    6. Wait until the packets are loop backed in the RX data path. Poll the RX_PKT_VALID bit to monitor the transmission status.
    7. Read RX packet data information from 0x110 - 0x112 registers in sequential order, starting with the 0x110 register. The PTP monitor logic refreshes the 0x110 - 0x112 registers content to next data when read from 0x112 register.
    8. Repeat the previous step until the RX_PKT_EOP bit is set to 1 indicating the read operation reached the end of the packet.
    9. Read RX ingress timestamp.
      1. Read the RX ingress timestamp from the 0x114 - 0x116 registers in sequential order, starting with the 0x14 register. The PTP monitor logic refreshes the 0x114 - 0x116 registers content to next data when read from 0x116 register.
    10. Display the TX packet content, RX packet content, TX PTP commands, TX egress timestamp, and RX ingress timestamp information.
    11. Display the comparison information. Note that in 1-step commands, the TX/RX packets and PTP commands field content is the same.
    12. Repeat steps b through step k until the system processes all packets.
      Note: The design example simulation performs step 14 for only first six packets to reduce long simulation time.
  14. Perform Avalon® memory-mapped interface test on PTP-related registers.
    • Selective PTP Assymmetry Delay and P2P MeanPathDelay registers
    • Selective Master TOD Avalon® memory-mapped interface registers
  15. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: Ethernet IP soft reset register
    • 0x214: TX MAC source address register [31:0]
    • 0x218: TX MAC source address register [47:32]
    • 0x21C: RX MAC frame size register
  16. Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.

The following sample output illustrates a successful simulation test.

--------------------
TX Packet #1
--------------------
----------------------------------------------------------
| | 0 1 2 3 4 5 6 7 8 9 A B C D E F |
----------------------------------------------------------
| 0000 | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F |
| 0010 | 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F |
| 0020 | 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F |
| 0030 | 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F |
| 0040 | 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F |
| 0050 | 50 51 52 53 54 55 56 57 |
----------------------------------------------------------
--------------------
RX Packet #1
--------------------
----------------------------------------------------------
| | 0 1 2 3 4 5 6 7 8 9 A B C D E F |
----------------------------------------------------------
| 0000 | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F |
| 0010 | 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F |
| 0020 | 20 21 22 23 24 25 26 27 00 00 2A 2B 2C 2D 2E 2F |
| 0030 | 30 31 32 33 34 35 36 37 AB CD 3A 3B 3C 3D 3E 3F |
| 0040 | 40 41 42 43 44 45 46 47 48 49 4A 4B 00 00 00 00 |
| 0050 | 00 23 45 67 89 AB 56 57 CC 12 34 CC |
----------------------------------------------------------
--------------------
TX PTP Command #1
--------------------
Egress Timestamp Request : 0
Insert Timestamp : 1
Update CorrectionField : 0
Clear UDP/IPv4 Checksum : 1
Update UPD/IPv6 Extended Bytes : 0
Add Peer-to-Peer (P2P) MinPathDelay : 0
Add Asymmetry Delay : 0
Asymmetry Delay Sign : 0
Asymmetry & P2P MinPathDelay Select : 123
Timestamp Field Offset : 0x004C
Correction Field Offset : 0x0032
Checksum Field Offset : 0x0028
Timestamp Fingerprint : 0x02
TX Ingress Timestamp : 0x0
--------------------
Timestamps #1
--------------------
TX Egress Timestamp : 0x000000000023456789AB7394
RX Ingress Timestamp : 0x000000000023456789BCDEF0
TX User Fingerprint : 0x02
TX Returned Fingerprint : 0x02
TX Egress Virtual Lane : 2
RX Ingress Virtual Lane : 2
--------------------
Comparison #1
--------------------
RX ITS - TX ETS : 0x116B5C / 17.419ns
TX Timestamp Fields : 0x4C4D4E4F505152535455
RX Timestamp Fields : 0x000000000023456789AB
TX Correction Fields : 0x3233343536373839
RX Correction Fields : 0x323334353637ABCD
TX Checksum Fields : 0x2829
RX Checksum Fields : 0x0000
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