F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/11/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel FPGA Hard IP Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Testing the Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel FPGA Hard IP Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4.4. QSF Assignments

For successful logic generation/compilation and simulation, you must specify lane location assignment and tile location assignment in the .qsf file in your design. The exact .qsf assignments are OPN-specific and must be updated for each OPN. For information about updating tile location, refer to Simulation.

This section provides an example of .qsf assignments for FGT and FHT PMA types for simulation.

Table 12.  FGT .qsf AssignmentsThe following .qsf assignments are specific to the AGIA027R29A1E2VR0 OPN. If you use a device with a different OPN, you must update these location assignments to match pin out of the corresponding OPN.
Ethernet Mode QSF Assignments
All -1 modes 
set_location_assignment PIN_FP74 -to i_refclk2pll
set_location_assignment PIN_GG78 -to o_tx_serial[0]
set_location_assignment PIN_GK83 -to i_rx_serial[0]
All -2 modes 
set_location_assignment PIN_FP74 -to i_refclk2pll
set_location_assignment PIN_GG78 -to o_tx_serial[0]
set_location_assignment PIN_GW80 -to o_tx_serial[1]
set_location_assignment PIN_GK83 -to i_rx_serial[0]
set_location_assignment PIN_HB83 -to i_rx_serial[1]
All -4 modes 
set_location_assignment PIN_FP74 -to i_refclk2pll
set_location_assignment PIN_GG78 -to o_tx_serial[0]
set_location_assignment PIN_GW80 -to o_tx_serial[1]
set_location_assignment PIN_HB77 -to o_tx_serial[2]
set_location_assignment PIN_HL80 -to o_tx_serial[3]
set_location_assignment PIN_GK83 -to i_rx_serial[0]
set_location_assignment PIN_HB83 -to i_rx_serial[1]
set_location_assignment PIN_HP83 -to i_rx_serial[2]
set_location_assignment PIN_JD80 -to i_rx_serial[3]
All -8 modes 
set_location_assignment PIN_FP74 -to i_refclk2pll
set_location_assignment PIN_GG78 -to o_tx_serial[0]
set_location_assignment PIN_GW80 -to o_tx_serial[1]
set_location_assignment PIN_HB77 -to o_tx_serial[2]
set_location_assignment PIN_HL80 -to o_tx_serial[3]
set_location_assignment PIN_HP77 -to o_tx_serial[4]
set_location_assignment PIN_JG77 -to o_tx_serial[5]
set_location_assignment PIN_JT74 -to o_tx_serial[6]
set_location_assignment PIN_JW77 -to o_tx_serial[7]
set_location_assignment PIN_GK83 -to i_rx_serial[0]
set_location_assignment PIN_HB83 -to i_rx_serial[1]
set_location_assignment PIN_HP83 -to i_rx_serial[2]
set_location_assignment PIN_JD80 -to i_rx_serial[3]
set_location_assignment PIN_JG83 -to i_rx_serial[4]
set_location_assignment PIN_JT80 -to i_rx_serial[5]
set_location_assignment PIN_JW83 -to i_rx_serial[6]
set_location_assignment PIN_KH80 -to i_rx_serial[7]
Table 13.  FHT .qsf AssignmentsThe following .qsf assignments are specific to the AGIA027R29A1E2VR0 OPN. If you use a device with a different OPN, you must update these location assignments to match pin out of the corresponding OPN.
Ethernet Mode QSF Assignments
All -1 modes 
set_location_assignment PIN_EC76 -to i_bk_refclk2pll
set_location_assignment PIN_HY68 -to i_refclk2pll
set_location_assignment PIN_DU82 -to o_tx_serial[0]
set_location_assignment PIN_DL78 -to i_rx_serial[0]
All -2 modes 
set_location_assignment PIN_EC76 -to i_bk_refclk2pll
set_location_assignment PIN_HY68 -to i_refclk2pll
set_location_assignment PIN_DU82 -to o_tx_serial[0]
set_location_assignment PIN_EK82 -to o_tx_serial[1]
set_location_assignment PIN_DL78 -to i_rx_serial[0]
set_location_assignment PIN_EC78 -to i_rx_serial[1]
All -4 modes 
set_location_assignment PIN_EC76 -to i_bk_refclk2pll
set_location_assignment PIN_HY68 -to i_refclk2pll
set_location_assignment PIN_DU82 -to o_tx_serial[0]
set_location_assignment PIN_EK82 -to o_tx_serial[1]
set_location_assignment PIN_FB82 -to o_tx_serial[2]
set_location_assignment PIN_FP82 -to o_tx_serial[3]
set_location_assignment PIN_DL78 -to i_rx_serial[0]
set_location_assignment PIN_EC78 -to i_rx_serial[1]
set_location_assignment PIN_ET78 -to i_rx_serial[2]
set_location_assignment PIN_FH78 -to i_rx_serial[3]
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