F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/11/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel FPGA Hard IP Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Testing the Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel FPGA Hard IP Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training

This design example describes necessary steps to enable auto-negotiation and link training (AN/LT) in your design example.

When you enable auto-negotiation and link training parameter in the IP and generate a design example, the design example instantiates two separate IPs, F-Tile Ethernet Intel FPGA Hard IP and the F-Tile Auto-Negotiation and Link Training for Ethernet. You must connect required signals at the top level of your testbench. To successfully simulate your design, you must specify appropriate tile placement assignments in the .qsf file. The tile placement assignment information is unique to each device's OPN.

The following IP parameter settings were used to generate this design example:
Table 10.   F-Tile Ethernet Intel FPGA Hard IP Parameter SettingsTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
General Options
PMA type FGT
Ethernet mode 100GE-4
Client interface MAC segmented
FEC mode IEEE 802.3 RS(528,514) (CL91)
PMA reference frequency 156.25 MHz
System PLL frequency 805.6640625 MHz
Table 11.   F-Tile Auto-Negotiation and Link Training for Ethernet Parameter SettingsTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
Mode Selection
Enable auto-negotiation on reset

On
Enable link training on reset

On
PMA type FGT
Ethernet mode 100GE-4
KR or CR mode KR mode
Number of ports 1
FEC mode IEEE 802.3 RS(528,514)
Status clock frequency 100 MHz

For more information about steps of how to generate a design example, refer to the Generating the Design Example.

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