HDMI Intel® FPGA IP User Guide

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ID 683798
Date 12/15/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10, and Intel® Agilex™ F-tile Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

6.1.10. HDCP 2.3 RX Architecture

The receiver block decrypts the protected video and auxiliary data from the connected HDCP 2.3 device. The HDCP 2.3 receiver block has identical structure layers as the HDCP 2.3 transmitter block.
Figure 52. Architecture Block Diagram of HDCP 2.3 RX IP

The HDCP 2.3 RX core is fully autonomous. For HDMI application, the transmitter drives the HDCP 2.3 RX core using the standard DDC interface supporting I2C protocol.

The HDCP specifications requires the HDCP 2.3 RX core to be programmed with the DCP-issued production key – Global Constant (lc128), RSA private key (kprivrx) and RSA Public Key Certificate (certrx). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement shown in the table below.

Table 56.  HDCP 2.3 RX Key Port Addressing
Address Content
8'hE3 lc128[127:96]
8'hE2 lc128[95:64]
8'hE1 lc128[63:32]
8'hE0 lc128[31:0]
8'hDF kprivrx_p[511:480]
... ...
8'hD0 kprivrx_p[31:0]
8'hCF kprivrx_q[511:480]
... ...
8'hC0 kprivrx_q[31:0]
8'hBF kprivrx_dp[511:480]
... ...
8'hB0 kprivrx_dp[31:0]
8'hAF kprivrx_dq[511:480]
... ...
8'hA0 kprivrx_dq[31:0]
8'h9F kprivrx_qinv[511:480]
... ...
8'h90 kprivrx_qinv[31:0]
8'h83–8'h8F Reserved
8'h82 {16’d0, certrx[4175:4160]}
8'h81 certrx[4159:4128]
... ...
8'h01 certrx[63:32]
8'h00 certrx[31:0]

The Video Stream and Auxiliary Layer receives audio and video content over its Video and Aux Data Input Port, and performs the decryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI IP to determine when to decrypt frames.

To implement the HDCP 2.3 RX core as a repeater upstream interface, the IP must propagate certain information such as ReceiverID List and RxInfo to the upstream transmitter and to be used for HMAC computation. The repeater downstream interface (TX) must provide this information using the Repeater Message Port (Avalon-MM). You can use the same clock source to drive the clocking for the HDCP Register Port and Repeater Message Port.

The RX registers mapping defined in the following table is equivalent to the address space for HDCP 2.3 receiver defined in the HDCP specification.

Table 57.  HDCP 2.3 RX Registers Mapping
Address Register R/W Reset Bit Bit Name Description
0x44 – 0x4F Rsvd RO 0x00 7:0 Reserved Reserved.
0x50 HDCP2VERSION RO 0x04 7:3 Reserved Reserved.
2 HDCP22 When set to 1, the core supports HDCP 2.2 and above.
1:0 Reserved Reserved.
0x51 – 0x5F Rsvd RO 0x00 7:0 Reserved Reserved.
0x60 WRITE_MESSAGE WO 0x00 7:0 WR_MSG Variable length message written by the transmitter as a single burst write to this address.
0x61 – 0x6F Rsvd RO 0x00 7:0 Reserved Reserved.
0x70 RXSTATUS0 RO 0x00 7:0 MSG_SIZE0 The lower part of message size in bytes available at the receiver for reading by the transmitter.
0x71 RXSTATUS1 RO 0x00 7:4 Reserved Reserved
3 REAUTH_REQ When set to 1, indicates the link integrity check failure at the receiver (including upstream side of the repeater) or the upstream side of the repeater has transitioned into an unauthenticated state. Self-cleared by the core on every new authentication initiated by the AKE_Init message.
2 READY When set to 1, the repeater has built the list of downstream Receiver IDs and computed the verification value V’. Self-cleared by the core as soon as the RepeaterAuth_Send_ReceiverID_List message has been read by the transmitter or on every new authentication request by the transmitter.
1:0 MSG_SIZE1 The upper part of message size in bytes available at the receiver for reading by the transmitter.
0x72 – 0x7F Rsvd RO 0x00 7:0 Reserved Reserved.
0x80 READ_MESSAGE RO 0x00 7:0 RD_MSG Variable length message read by the transmitter as a single burst read from this address.
0x81 – 0xBF Rsvd RO 0x00 7:0 Reserved Reserved.
0xC0 – 0xFF DBG RW 0x00 7:0 DBG_REGS Implemented specific debug registers.
Table 58.  HDCP 2.3 RX Repeater Registers Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 RPT_RCVDID_LIST WO 0x00000000 31:8 Reserved Reserved
7:0 RCVDID_LIST Byte write ReceiverID_List in big endian order.
0x01 RPT_RXINFO RW 0x00000000 31:19 Reserved Reserved
18 REQUEST Read-only. Asserted by the core to request for RCVDID_LIST and RXINFO. This usually happens when re-authentication is triggered by the connected upstream. Note that when REQUEST is asserted, the READY should also be asserted.
17 READY Read-only. Asserted by the core to indicate RCVDID_LIST and RXINFO are processed. Write RCVDID_LIST and RXINFO after this bit is asserted.
16 VALID Set to 1 after RCVDID_LIST and RXINFO are written. Self-cleared by the core after RCVDID_LIST and RXINFO are read.
15:0 RXINFO

[15:12]: Reserved.

[11:9]: DEPTH

[8:4]: DEVICE_COUNT

[3]: MAX_DEVS_EXCEEDED

[2]: MAX_CASCADE_EXCEEDED

[1]: HDCP2_REPEATER_DOWNSTREAM

[0]: HDCP1_DEVICE_DOWNSTREAM

0x02 RPT_TYPE RO 0x00000000 31:9 Reserved Reserved
8 VALID Asserted by the core to indicate content stream TYPE is valid. Self-cleared by the core after TYPE is read.
7:0 TYPE

0x00: Type 0 Content Stream

0x01: Type 1 Content Stream

0x02-0xFF: Reserved. Treated as Type 1 Content Stream.
0x03 RPT_MISC RW 0x00000000 31:1 Reserved Reserved.
0 REPEATER

Set to 0 if no downstream is connected or if the connected downstream is not HDCP 2.3-capable. This means the receiver IP core is an end-point receiver rather than a repeater.

Set to 1 if the connected downstream is HDCP- capable.

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