Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis
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Ixiasoft
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1.11.4.2.2. Creating Multiple Intel® Quartus® Prime Projects for a Bottom-Up Incremental Compilation Flow
Designers should create a LogicLock region to create a design floorplan for each block to avoid conflicts between partitions. The top-level designer then imports all the blocks and assignments into the top-level project. This method allows each block in the design to be optimized separately and then imported into one top-level project.