Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

Download PDF
ID 683796
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Synopsys Synplify* Support 2. Mentor Graphics Precision* Synthesis Support A. Intel® Quartus® Prime Standard Edition User Guides
1. Synopsys Synplify* Support x
1.1. About Synplify Support 1.2. Design Flow 1.3. Hardware Description Language Support 1.4. Intel Device Family Support 1.5. Tool Setup 1.6. Synplify Software Generated Files 1.7. Design Constraints Support 1.8. Simulation and Formal Verification 1.9. Synplify Optimization Strategies 1.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 1.11. Incremental Compilation and Block-Based Design 1.12. Synopsys Synplify* Support Revision History
1.5. Tool Setup x
1.5.1. Specifying the Intel® Quartus® Prime Software Version 1.5.2. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration
1.5.2. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration x
1.5.2.1. Running the Intel® Quartus® Prime Software from within the Synplify Software 1.5.2.2. Using the Intel® Quartus® Prime Software to Run the Synplify Software
1.7. Design Constraints Support x
1.7.1. Running the Intel® Quartus® Prime Software Manually With the Synplify-Generated Tcl Script 1.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software
1.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software x
1.7.2.1. Individual Clocks and Frequencies 1.7.2.2. Input and Output Delay 1.7.2.3. Multicycle Path 1.7.2.4. False Path
1.9. Synplify Optimization Strategies x
1.9.1. Using Synplify Premier to Optimize Your Design 1.9.2. Using Implementations in Synplify Pro or Premier 1.9.3. Timing-Driven Synthesis Settings 1.9.4. FSM Compiler 1.9.5. Optimization Attributes and Options 1.9.6. Intel-Specific Attributes
1.9.3. Timing-Driven Synthesis Settings x
1.9.3.1. Clock Frequencies 1.9.3.2. Multiple Clock Domains 1.9.3.3. Input and Output Delays 1.9.3.4. Multicycle Paths 1.9.3.5. False Paths
1.9.4. FSM Compiler x
1.9.4.1. FSM Explorer in Synplify Pro and Premier
1.9.5. Optimization Attributes and Options x
1.9.5.1. Retiming in Synplify Pro and Premier 1.9.5.2. Maximum Fan-Out 1.9.5.3. Preserving Nets 1.9.5.4. Register Packing 1.9.5.5. Resource Sharing 1.9.5.6. Preserving Hierarchy 1.9.5.7. Register Input and Output Delays 1.9.5.8. syn_direct_enable 1.9.5.9. I/O Standard
1.9.6. Intel-Specific Attributes x
1.9.6.1. altera_chip_pin_lc 1.9.6.2. altera_io_powerup 1.9.6.3. altera_io_opendrain
1.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
1.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog 1.10.2. Including Files for Intel® Quartus® Prime Placement and Routing Only 1.10.3. Inferring Intel FPGA IP Cores from HDL Code
1.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog x
1.10.1.1. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files 1.10.1.2. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files 1.10.1.3. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores 1.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor 1.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files 1.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files 1.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
1.10.3. Inferring Intel FPGA IP Cores from HDL Code x
1.10.3.1. Inferring Multipliers 1.10.3.2. Inferring RAM 1.10.3.3. RAM Initialization 1.10.3.4. Inferring ROM 1.10.3.5. Inferring Shift Registers
1.10.3.1. Inferring Multipliers x
1.10.3.1.1. Resource Balancing 1.10.3.1.2. Controlling the DSP Block Inference 1.10.3.1.3. Signal Level Attribute
1.11. Incremental Compilation and Block-Based Design x
1.11.1. Design Flow for Incremental Compilation 1.11.2. Creating a Design with Separate Netlist Files for Incremental Compilation 1.11.3. Using MultiPoint Synthesis with Incremental Compilation 1.11.4. Creating Multiple .vqm Files for a Incremental Compilation Flow With Separate Synplify Projects 1.11.5. Performing Incremental Compilation in the Intel® Quartus® Prime Software
1.11.3. Using MultiPoint Synthesis with Incremental Compilation x
1.11.3.1. Set Compile Points and Create Constraint Files 1.11.3.2. Additional Considerations for Compile Points 1.11.3.3. Creating a Intel® Quartus® Prime Project for Compile Points and Multiple .vqm Files
1.11.3.1. Set Compile Points and Create Constraint Files x
1.11.3.1.1. Defining Compile Points With .tcl or .sdc Files
1.11.3.3. Creating a Intel® Quartus® Prime Project for Compile Points and Multiple .vqm Files x
1.11.3.3.1. Creating a Single Intel® Quartus® Prime Project for a Standard Incremental Compilation Flow 1.11.3.3.2. Creating Multiple Intel® Quartus® Prime Projects for a Bottom-Up Incremental Compilation Flow
1.11.4. Creating Multiple .vqm Files for a Incremental Compilation Flow With Separate Synplify Projects x
1.11.4.1. Manually Creating Multiple .vqm Files With Black Boxes 1.11.4.2. Creating a Intel® Quartus® Prime Project for Multiple .vqm Files
1.11.4.1. Manually Creating Multiple .vqm Files With Black Boxes x
1.11.4.1.1. Creating Multiple .vqm Files for this Design 1.11.4.1.2. Creating Black Boxes in Verilog HDL 1.11.4.1.3. Creating Black Boxes in VHDL
1.11.4.2. Creating a Intel® Quartus® Prime Project for Multiple .vqm Files x
1.11.4.2.1. Creating a Single Intel® Quartus® Prime Project for a Standard Incremental Compilation Flow 1.11.4.2.2. Creating Multiple Intel® Quartus® Prime Projects for a Bottom-Up Incremental Compilation Flow
2. Mentor Graphics Precision* Synthesis Support x
2.1. About Precision RTL Synthesis Support 2.2. Design Flow 2.3. Intel Device Family Support 2.4. Precision Synthesis Generated Files 2.5. Creating and Compiling a Project in the Precision Synthesis Software 2.6. Mapping the Precision Synthesis Design 2.7. Synthesizing the Design and Evaluating the Results 2.8. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration 2.9. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 2.10. Incremental Compilation and Block-Based Design 2.11. Mentor Graphics Precision* Synthesis Support Revision History
2.2. Design Flow x
2.2.1. Timing Optimization
2.6. Mapping the Precision Synthesis Design x
2.6.1. Setting Timing Constraints 2.6.2. Setting Mapping Constraints 2.6.3. Assigning Pin Numbers and I/O Settings 2.6.4. Assigning I/O Registers 2.6.5. Disabling I/O Pad Insertion 2.6.6. Controlling Fan-Out on Data Nets
2.6.5. Disabling I/O Pad Insertion x
2.6.5.1. Preventing the Precision Synthesis Software from Adding I/O Pads 2.6.5.2. Preventing the Precision Synthesis Software from Adding an I/O Pad on an Individual Pin
2.7. Synthesizing the Design and Evaluating the Results x
2.7.1. Obtaining Accurate Logic Utilization and Timing Analysis Reports
2.8. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration x
2.8.1. Running the Intel® Quartus® Prime Software from within the Precision Synthesis Software 2.8.2. Running the Intel® Quartus® Prime Software Manually Using the Precision Synthesis‑Generated Tcl Script 2.8.3. Using the Intel® Quartus® Prime Software to Run the Precision Synthesis Software 2.8.4. Passing Constraints to the Intel® Quartus® Prime Software
2.8.4. Passing Constraints to the Intel® Quartus® Prime Software x
2.8.4.1. create_clock 2.8.4.2. set_input_delay 2.8.4.3. set_output_delay 2.8.4.4. set_max_delay and set_min_delay 2.8.4.5. set_false_path 2.8.4.6. set_multicycle_path
2.9. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features x
2.9.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files 2.9.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files 2.9.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor 2.9.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files 2.9.5. Instantiating Black Box IP Functions With Generated VHDL Files 2.9.6. Inferring Intel FPGA IP Cores from HDL Code
2.9.6. Inferring Intel FPGA IP Cores from HDL Code x
2.9.6.1. Multipliers 2.9.6.2. Setting the Use Dedicated Multiplier Option 2.9.6.3. Setting the dedicated_mult Attribute 2.9.6.4. Multiplier-Accumulators and Multiplier-Adders 2.9.6.5. Controlling DSP Block Inference 2.9.6.6. RAM and ROM
2.9.6.1. Multipliers x
2.9.6.1.1. Controlling DSP Block Inference for Multipliers
2.10. Incremental Compilation and Block-Based Design x
2.10.1. Creating a Design with Precision RTL Plus Incremental Synthesis 2.10.2. Creating Multiple Mapped Netlist Files With Separate Precision Projects or Implementations 2.10.3. Creating Black Boxes to Create Netlists 2.10.4. Creating Intel® Quartus® Prime Projects for Multiple Netlist Files 2.10.5. Hierarchy and Design Considerations
2.10.1. Creating a Design with Precision RTL Plus Incremental Synthesis x
2.10.1.1. Creating Partitions with the incr_partition Attribute
2.10.3. Creating Black Boxes to Create Netlists x
2.10.3.1. Creating Black Boxes in Verilog HDL Verilog HDL Black Box for Top-Level File A.v 2.10.3.2. Creating Black Boxes in VHDL
2.10.4. Creating Intel® Quartus® Prime Projects for Multiple Netlist Files x
2.10.4.1. Creating a Single Intel® Quartus® Prime Project for a Standard Incremental Compilation Flow 2.10.4.2. Creating Multiple Intel® Quartus® Prime Projects for a Bottom-Up Flow
1. Synopsys Synplify* Support
2. Mentor Graphics Precision* Synthesis Support
A. Intel® Quartus® Prime Standard Edition User Guides

2.10.3.1. Creating Black Boxes in Verilog HDL

Any design block that is not defined in the project or included in the list of files to be read for a project is treated as a black box by the software. In Verilog HDL, you must provide an empty module declaration for any module that is treated as a black box.

A black box for the top-level file A.v is shown in the following example. Provide an empty module declaration for any lower‑level files, which also contain a black box for any module beneath the current level of hierarchy.

Verilog HDL Black Box for Top-Level File A.v

module A (data_in, clk, e, ld, data_out);
   input data_in, clk, e, ld;
   output [15:0] data_out;
   wire [15:0] cnt_out;
   B U1 (.data_in (data_in),.clk(clk), .ld (ld),.data_out(cnt_out));
   F U2 (.d(cnt_out), .clk(clk), .e(e), .q(data_out));
   // Any other code in A.v goes here.
endmodule
//Empty Module Declarations of Sub-Blocks B and F follow here.
// These module declarations (including ports) are required for black boxes.
module B (data_in, clk, ld, data_out);
   input data_in, clk, ld;
   output [15:0] data_out;
endmodule
module F (d, clk, e, q);
   input [15:0] d;
   input clk, e;
   output [15:0] q;
endmodule
Level Two Title