AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

ID 683785
Date 5/13/2016
Public

1.8.2. ToD Interface Signals

Table 7.  ToD Interface SignalsThe Master and Slave ToDs are one of the components in the design with the IEEE 1588v2 feature.
Signal Direction Width Description
master_pulse_per_second Out 1 Pulse per second, the output from the Master PPS module. This signal asserts for 10ms.
start_tod_sync[] In NUM_CHANNELS Assert the respective signal bit to start TOD synchronization process for the channel. The synchronization process continues as long as this signal stays asserted.
pulse_per_second_10g[] Out NUM_CHANNELS Pulse per second for each channel, the output from10G PPS module. This signals asserts for 10ms.
pulse_per_second_1g[] Out NUM_CHANNELS Pulse per second for each channel, the output from1G PPS module. This signals asserts for 10ms.