Altera Triple-Speed Ethernet IP core |
Provides the MAC and PCS functionalities and features. |
I2C Controller |
Monitors and controls the SFP module. This controller consists of the optics_control and i2c_iopad modules. |
Traffic Controller |
Generates and monitors Ethernet packets for hardware verification. |
Altera JTAG Avalon Master |
Provides an interface to the Qsys tool for users to initiate Avalon Memory-Mapped transactions through System Console. |
Address Decoder Top |
The address decoder module for the design. |
Address Decoder Channel |
The address decoder module for each component within the channel. |
Address Decoder Multi-Channel |
The address decoder module for all channels and the components used for all channels, such as the Master TOD. |
Reset Controller |
Synchronizes the reset of all design components. |
fPLL |
Generates the tx_serial_clk, pcs_phase_measure_clk, and tod_sync_sampling_clk clocks for the designs. |
Components for the IEEE 1588v2 feature |
Master Time-of-Day (TOD) |
The master time-of-day for all channels. |
TOD Synch |
Synchronizes the time-of-day from the Master TOD module to the Local TOD module for all channels. |
Local TOD |
The time-of-day module for each channel. |
Pulse per Second Module |
Returns the pulse per second (pps) value for all channels. |
PTP Packet Classifier |
Decodes the packet type of each incoming PTP packet and returns the information to the Triple-Speed Ethernet IP core. |