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Ixiasoft
1.7. Testbench
You can use the provided testbench to verify the reference designs. The testbench loops back Ethernet packet into the designs.
Figure 4. Testbench Block Diagram
Component | Description |
---|---|
Device under test (DUT) | The reference design. |
Avalon driver | Consists of Avalon Streaming (Avalon-ST) master bus functional models (BFMs) to generate and monitor ethernet packets. The driver also connects with the design components through the Avalon Memory-Mapped (Avalon-MM) interface. |
Ethernet packet monitors | Monitor transmit and receive datapaths, and display the frames in the simulator console. |