1.2.9. Signals
Signal | Clock Domain | Direction | Description |
---|---|---|---|
Clocks and Resets | |||
refclk_core | — | Input | Reference clock for FPGA core modules. |
refclk_xcvr | — | Input | Reference clock for transceiver PHY. |
mgmt_clk | — | Input | Reference clock for all peripherals connected via Avalon® memory-mapped interconnect. |
global_rst_n | mgmt_clk | Input | Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk. |
Signal |
Clock Domain |
Direction |
Description |
Serial Data | |||
rx_serial_data[LINK*L-1:0] | refclk_xcvr | Input | Differential high speed serial input data. The clock is recovered from the serial data stream. |
tx_serial_data[LINK*L-1:0] | refclk_xcvr | Output | Differential high speed serial output data. The clock is embedded in the serial data stream. |
Signal |
Clock Domain |
Direction |
Description |
JESD204B | |||
sysref_out | mgmt_clk | Output | SYSREF signal for JESD204B Subclass 1 implementation. |
sync_n_out | link_clk | Output | Indicates a SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting. |
tx_link_error | link_clk | Output | Error interrupt from JESD204B IP core indicating TX link error |
rx_link_error | link_clk | Output | Error interrupt from JESD204B IP core indicating RX link error |
Signal |
Clock Domain |
Direction |
Description |
Avalon® Streaming User Data | |||
avst_usr_din[LINK*TL_DATA_BUS_WIDTH-1:0] | frame_clk | Input | TX data from the Avalon® streaming source interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
|
avst_usr_din_valid[LINK-1:0] | frame_clk | Input | Indicates whether the data from the Avalon® streaming source interface to the transport layer is valid or invalid.
|
avst_usr_din_ready[LINK-1:0] | frame_clk | Output | Indicates that the transport layer is ready to accept data from the Avalon® streaming source interface.
|
avst_usr_dout[LINK*TL_DATA_BUS_WIDTH-1:0] | frame_clk | Output | RX data to the Avalon® streaming sink interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
|
avst_usr_dout_valid[LINK-1:0] | frame_clk | Output | Indicates whether the data from the transport layer to the Avalon® streaming sink interface is valid or invalid.
|
avst_usr_dout_ready[LINK-1:0] | frame_clk | Input | Indicates that the Avalon® streaming sink interface is ready to accept data from the transport layer.
|
avst_patchk_data_error [LINK-1:0] | frame_clk | Output | Output signal from pattern checker indicating a pattern check error. |
Signal |
Clock Domain |
Direction |
Description |
SPI | |||
spi_MISO 5 | spi_SCLK | Input | Input data from external slave to the master. |
spi_MOSI 5 | spi_SCLK | Output | Output data from the master to the external slaves. |
spi_SDIO 6 | spi_SCLK | Input/Output | Output data from the master to external slave. Input data from external slave to master |
spi_SCLK | mgmt_clk | Output | Clock driven by the master to slaves, to synchronize the data bits. |
spi_SS_n[2:0] | spi_SCLK | Output | Active low select signal driven by the master to individual slaves, to select the target slave. Defaults to 3 bits. |