1.2.5.1. Platform Designer System Component
The Platform Designer system instantiates the JESD204B IP core data path and supporting peripherals.
Figure 10. Platform Designer System for System Console Control Design Example for Intel® Stratix® 10 L-Tile and H-Tile Devices
Figure 11. Platform Designer System for System Console Control Design Example for Intel® Stratix® 10 E-Tile Devices
The top level Platform Designer system instantiates the following modules:
- Platform Designer system
- JESD204B subsystem
- JTAG to Avalon® master bridge
- Parallel I/O (PIO)
- ATX PLL (Applicable only for Intel® Stratix® 10 L-tile and H-tile devices)
- Core PLL
- Serial Port Interface (SPI)—master module
The following are the key features of the top level Platform Designer system:
- Supports System Console control design example
- Supports 3 data path types:
- Duplex—Both TX and RX data paths present
- Simplex TX—Only TX data path present
- Simplex RX—Only RX data path present
- The JESD204B subsystem, parallel I/O and SPI master modules are connected to the JTAG to Avalon® master bridge module via the Avalon® memory-mapped interface.
- JTAG to Avalon® master bridge provides a link to the user via System Console. You can control the behavior of the design example via Tcl scripts executed in the System Console interface.
- TX data path flow:
- Input: 32-bit per transceiver lane Avalon® streaming input from assembler (TX transport layer)
- Output: TX serial data
- RX data path flow:
- Input: RX serial data from either external converter source or internal serial loopback
- Output: 32-bit per transceiver lane Avalon® streaming output to deassembler (RX transport layer)
- SPI master module links out to the SPI configuration interface of external converters via a 3- or 4-wire SPI interconnect (depending on Generate 3-Wire SPI Module setting).
- SPI master module handles the serial transfer of configuration data to the SPI interface on the converter end
- The ATX PLL generates the serial clock for clocking the TX serial data (ATX PLL is applicable only for Intel® Stratix® 10 L-tile and H-tile devices)
- ATX PLL module generated for duplex and simplex TX data path only
- The core PLL generates the following clocks for the system:
- Link clock
- Frame clock
Figure 12. Top Level Platform Designer Address Map for Intel® Stratix® 10 L-Tile and H-Tile Devices
Figure 13. Top Level Platform Designer Address Map for Intel® Stratix® 10 E-Tile Devices
JESD204B Subsystem in Platform Designer
The JESD204B subsystem instantiates the following modules:
- JESD204B Intel® FPGA IP
- Reset sequencer
- Transceiver PHY reset controller
- Avalon® memory-mapped bridge
JESD204B IP
The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon® memory-mapped interconnect. The JESD204B IP core uses three separate Avalon® memory-mapped ports:
- Base core TX data path—For accessing the TX CSR
- Base core RX data path—For accessing the RX CSR
- PHY layer—For accessing the transceiver PHY CSR
The structure of the design example varies depending on the values of these JESD204B IP core parameters:
- Data path:
- Duplex—Both TX and RX data paths and CSR interfaces present
- TX only—Only TX data path and CSR interface present
- RX only—Only RX data path and CSR interface present
Reset Sequencer
The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:
- Core PLL reset—resets the core PLL
- Transceiver reset—resets the JESD204B IP core PHY module
- TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
- TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer
- TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules
The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via Avalon® memory-mapped interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.
Figure 14. Reset Sequence
Note: For Intel® Stratix® 10 L-tile and H-tile devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready. The reset staggering may incur long simulation time. You may observe the staggering of TX and RX reset through tx_analogreset_stat, tx_digitalreset_stat, rx_analogreset_stat, and rx_digitalreset_stat respectively.
Transceiver PHY Reset Controller
The transceiver PHY reset controller is a standard Platform Designer component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.
The transceiver PHY reset controller is applicable only for Intel® Stratix® 10 L-tile and H-tile devices. On the other hand, the Intel® Stratix® 10 E-tile devices have a configurable reset controller embedded in the E-tile transceiver PHY module, which makes use of individual reset counters to control reset timing for the various reset outputs.
Avalon® Memory-Mapped Bridge
All the Avalon® memory-mapped submodules in the JESD204B subsystem are connected via Avalon® memory-mapped interconnect to a single Avalon® memory-mapped bridge. This bridge is the single interface for Avalon® memory-mapped communications into and out of the subsystem.
JESD204B Subsystem Address Map
Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window.
Figure 15. JESD204B Subsystem Address Map for Intel® Stratix® 10 L-Tile and H-Tile Devices
Figure 16. JESD204B Subsystem Address Map for Intel® Stratix® 10 E-Tile Devices
JTAG to Avalon® Master Bridge
The JTAG to Avalon® master bridge is a standard Platform Designer component in the IP Catalog standard library. This module provides a connection between a host system and the Platform Designer system via the respective physical interfaces; JTAG on the host system end and Avalon® memory-mapped on the Platform Designer system end. Host systems can initiate Avalon® memory-mapped transactions by sending encoded streams of bytes via JTAG interface. The module supports reads and writes, but not burst transactions.
Parallel I/O
Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon® master (JTAG to Avalon® master bridge). There are two sets of 32-bit PIO registers:
- Status registers—input from the HDL components to the Avalon® master
- Control registers—output from the Avalon® master to the HDL components
The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.
| Bit | Signal |
|---|---|
| 0 | Core PLL locked |
| 1 | TX transceiver ready (for duplex and simplex TX data path only) |
| 2 | RX transceiver ready (for duplex and simplex RX data path only) |
| 3 | Test pattern checker data error (for duplex and simplex RX data path only) |
| 4 | TX link error (for duplex and simplex TX data path only) |
| 5 | RX link error (for duplex and simplex RX data path only) |
| 6 | All TX PMA ready (for duplex and simplex TX data path only) |
| 7 | All RX PMA ready (for duplex and simplex RX data path only) |
| 31 | 0: Indicates H-tile or L-tile 1: Indicates E-tile |
| Bit | Signal |
|---|---|
| 0 | TX to RX serial loopback path enable (for Intel® Stratix® 10 L-tile and H-tile duplex data path only) |
| 30 | Global reset |
| 31 | SYSREF |
ATX PLL
Note: This module is only available in the Intel® Stratix® 10 L-tile or H-tile design example when the duplex or simplex TX data path option is selected.
The ATX PLL is a standard Platform Designer component in the IP Catalog standard library. This module supplies a low-jitter serial clock to the transceiver PHY module. The reference clock input to the ATX PLL comes from an external source.
For simplex TX variant, the frequency selection in the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP parameter editor is disabled. The design example generates the ATX PLL with the reference clock frequency of either:
- Hard PCS: data_rate/20
- Soft PCS: data_rate/40
Refer to Changing the Data Rate or Reference Clock Frequency for more information about modifying the ATX PLL reference clock frequency to suit your application.
For duplex variant, the ATX PLL and CDR share the same reference clock pin. You must select the frequency from the PLL/CDR Reference Clock Frequency drop-down list in the IP parameter editor.
For the ATX PLL reference clock frequencies supported range, refer to the Intel® Stratix® 10 Device Datasheet.
Core PLL
The core PLL module generates the clocks for the FPGA core fabric. An IOPLL module is instantiated as core PLL.
The core PLL uses an external clock input as its reference clock to generate two derivative clocks from a single VCO:
- Link clock
- Frame clock
| Clock | Formula | Description |
|---|---|---|
| Link Clock | Serial data rate/40 | The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer. |
| Frame Clock | Derived based on settings; refer to Table 14. | The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric. |
For the frame clock, when the F parameter is 1, 2 or 3, the resulting frame clock frequency easily exceeds the capability of the core PLL to generate and close timing. The top level RTL file, (altera_jesd204_ed_<data path>.sv), defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). F = 3 uses a constant division factor of 2. This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly.
Note: For JESD204B IP design examples, F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2.
These examples show how to derive the frame clock frequency:
Example 1: The actual frame clock for a serial data rate of 10 Gbps and F = 1 is:
(10000/(10 × 1)) / F1_FRAMECLK_DIV = 1000 / 4 = 250 MHzExample 2: The actual frame clock for a serial data rate of 6 Gbps and F = 3 is:
(6000/(10 × 3)) / 2 = 200 / 2 = 100 MHzFrame Clock and Link Clock Relationship
The frame clock and link clock are synchronous. For the derived F mode, the ratio of link_clk period to frame_clk period is given by this formula:
link_clk period to frame_clk period ratio = 32xL/(MxSxN')| F Parameter | fTXframe(txframe_clk frequency) | fRXframe(rxframe_clk frequency) |
|---|---|---|
| 1 | fTXlinkx(4/F1_FRAMECLK_DIV) | fRXlinkx(4/F1_FRAMECLK_DIV) |
| 2 | fTXlinkx(2/F2_FRAMECLK_DIV) | fRXlinkx(2/F2_FRAMECLK_DIV) |
| 3 | fTXlinkx(2/3) | fRXlinkx(2/3) |
| 4 | fTXlink | fRXlink |
| 8 | fTXlink/2 | fRXlink/2 |
Note: The IOPLL is generated with the Use Nondedicated Feedback Path option being disabled (default setting). You can turn on the Use Nondedicated Feedback Path option in the IP parameter editor to utilize the clock resources efficiently after the design example is successfully generated. Refer to the Clock Feedback Modes section of Intel® Stratix® 10 Clocking and PLL User Guide for more information about this option.
SPI Master
The SPI master module is a standard Platform Designer component in the IP Catalog standard library. This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, external clock modules) via a structured register space inside the converter device. The SPI master has an Avalon® memory-mapped interface that connects to the Avalon® master (JTAG to Avalon® master bridge) via the Avalon® memory-mapped interconnect and can receive configuration instructions from the Avalon® master.
This module is configured to a 4-wire, 24-bit width interface. If the Generate 3-Wire SPI Module option is selected, an additional module is instantiated to convert the 4-wire output of the SPI master to 3-wire.
For more details on the SPI master module, refer to the JESD204B Intel® FPGA IP User Guide.