JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1.1. Directory Structure

The JESD204B design example directories contain generated files for the design examples.
Figure 2. Directory Structure for the JESD204B Design Example
Table 1.  Directory and File Description
Directory/File Description
ed_sim The folder that contains simulation testbench files.
ed_sim/testbench/models The folder that contains the testbench and source files.
ed_sim/testbench/setup_scripts The folder that contains the test flow setup scripts.
ed_sim/testbench/pattern The folder that contains the source files for the pattern generator/checker.
ed_sim/testbench/transport_layer The folder that contains the source files for the transport layer.
ed_sim/testbench/aldec The folder that contains the test flow run scripts for Riviera-PRO* simulator. Also serves as the working directory for the simulator.
ed_sim/testbench/xcelium The folder that contains the test flow run scripts for Xcelium* Parallel simulator. Also serves as the working directory for the simulator.
ed_sim/testbench/mentor The folder that contains the test flow run scripts for ModelSim* or QuestaSim* simulator. Also serves as the working directory for the simulator.
ed_sim/testbench/synopsys/vcs The folder that contains the test flow run scripts for VCS* simulator. Also serves as the working directory for the simulator.
ed_sim/testbench/synopsys/vcsmx The folder that contains the test flow run scripts for VCS* MX simulator. Also serves as the working directory for the simulator.
ed_synth The folder that contains design example synthesizable components.
ed_synth/ip The folder that contains Platform Designer-instantiated IP modules.
ed_synth/altjesd_ed_qsys_<data path> The folder that contains Platform Designer-generated modules from the altjesd_ed_qsys_<data path>.qsys system.
ed_synth/altjesd_ss_<data path> The folder that contains Platform Designer-generated modules from the altjesd_ss_<data path>.qsys system.
ed_synth/pattern The folder that contains the source files for the pattern generator/checker.
ed_synth/transport_layer The folder that contains the source files for the transport layer.

ed_synth/altera_jesd204_ed_<data path>.qpf

ed_synth/altera_jesd204_ed_<data path>.qsf

Intel® Quartus® Prime project and settings files.
ed_synth/altjesd_ed_qsys_<data path>.qsys Platform Designer top level system.
ed_synth/altjesd_ss_<data path>.qsys Platform Designer subsystem.
ed_synth/altera_jesd204_ed_<data path>.sv Top level HDL source file.
ed_synth/altera_jesd204_ed_<data path>.sdc Top level design constraints file.
ed_synth/system_console The folder that contains all files necessary to run scripts in System Console (See Design Example Files for more details on folder content).
*.v Miscellaneous source files
ip_sim The folder that contains the simulation script to generate the JESD204B IP core Verilog/VHDL simulation model.
Level Two Title