JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1.4. Compiling and Testing the Design

The JESD204B parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  3. If you are performing external loopback test:
    • For designs targeting Intel® Stratix® 10 GX FPGA Development Kit (H-tile), attach the FMC loopback card to the FMC port A connector.
    • For designs targeting Intel® Stratix® 10 TX Signal Integrity Development Kit (E-tile), attach the respective loopback module according to the board revision and channel bonding mode.
      • For engineering sample (ES) edition (Revision A) and non-bonded channel configuration, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector.
      • For production edition (Revision B) and non-bonded channel configuration, attach the FMC+ loopback module at the FMC+ connector.
      • For production edition (Revision B) and bonded channel configuration, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector.
  4. Power-on the board.
  5. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Note: For more information about using the Clock Control application, refer to the Intel® Stratix® 10 GX FPGA Development Kit User Guide if you select Stratix 10 FPGA Development Kit or the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide if you select Stratix 10 TX Signal Integrity Development Kit - E-tile.
    Table 3.  Clock Setting
    Clock Name Clock Frequency
    refclk_xcvr Select the frequencies in the PLL/CDR Reference Clock Frequency drop down menu of the IP parameter editor.
    refclk_core
    mgmt_clk 100 MHz
    Figure 4.  Intel® Stratix® 10 GX FPGA Development Kit Clock Control GUI SettingThis example shows the clock control GUI setting for 6.144 Gbps data rate applied to H-tile devices with Intel® Stratix® 10 GX FPGA Development Kit.
    Figure 5.  Intel® Stratix® 10 TX Signal Integrity Development Kit Clock Control GUI Setting for Non-Bonded Mode DesignThis example shows the clock control GUI setting for a design example with non-bonded configuration. This design example is running at 6.144 Gbps on E-tile devices with Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (applies to Revision A and Revision B).
    Figure 6.  Intel® Stratix® 10 TX Signal Integrity Development Kit Clock Control GUI Setting for Bonded Mode DesignThis example shows the clock control GUI setting for a design example with bonded configuration. This design example is running at 6.144 Gbps on E-tile devices with Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (applies to Revision B).
  6. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
    Note: The generated design contains VID assignments that work for the Intel® Stratix® 10 GX FPGA development board and Intel® Stratix® 10 TX Signal Integrity development board. If your design is targeting to a VID part in other boards, you need to configure the VID parameters correctly by referring to the Intel® Stratix® 10 Power Management and VID Interface Implementation Guide section in the Intel® Stratix® 10 Power Management User Guide. You may ignore the VID assignments if your design is targeting non-VID device parts.

Section Content
Board Connectivity
Hardware Test for System Console Control Design Example

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