1.1.4.1. Board Connectivity
Refer to the instructions in Generating the Design.
Port Name | Port Description | Board Component | Component Description |
---|---|---|---|
global_rst_n | Global reset | S5 | User PB0 push-button |
refclk_xcvr | Transceiver reference clock input | U7 | Si5341 clock generator (OUT4) |
refclk_core | Core PLL reference clock input | U7 | Si5341 clock generator (OUT7) |
mgmt_clk | Control clock | U9 | Si5338 clock generator (CLK1) |
tx_serial_data | TX serial data | J13 | FMC port A connector |
rx_serial_data | RX serial data | J13 | FMC port A connector |
Port Name | Port Description | Board Component | Component Description |
---|---|---|---|
global_rst_n | Global reset | S8 | S8 push-button |
refclk_xcvr | Transceiver reference clock input | Engineering sample version board revision A (non-bonded channels) and production version board revision B (non-bonded channels) | |
U3 | Si5341 clock generator (OUT8) | ||
Production version board revision B (bonded channels) | |||
U3 | Si5341 clock generator (OUT4) | ||
refclk_core | Core PLL reference clock input | U3 | Si5341 clock generator (OUT2) |
mgmt_clk | Control clock | U3 | Si5341 clock generator (OUT3) |
tx_serial_data | TX serial data | Engineering sample version board revision A (non-bonded, up to 4 channels) | |
U32-1 | Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector) |
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Engineering sample version board revision A (non-bonded, 5–8 channels) | |||
U32-1 and U75-1 | Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector) |
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Production version board revision B (non-bonded, up to 8 channels) | |||
J27D | Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector) |
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Production version board revision B (bonded, up to 4 channels) | |||
U75-1 | Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector) |
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Production version board revision B (bonded, 5–8 channels) | |||
U32-1 and U75-1 | Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector |
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rx_serial_data | RX serial data | Engineering sample version board revision A (non-bonded, up to 4 channels) | |
U32-1 | Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector) |
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Engineering sample version board revision A (non-bonded, 5–8 channels) | |||
U32-1 and U75-1 | Intel® Stratix® 10 E-tile banks – 8B (QSFP-DD 1x2 connector) |
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Production version board revision B (non-bonded, up to 8 channels) | |||
J27D | Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector) |
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Production version board revision B (bonded, up to 4 channels) | |||
U75-1 | Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector) |
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Production version board revision B (bonded, 5–8 channels) | |||
U32-1 and U75-1 | Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector) |