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2.1. Installation and Licensing for LL 40GbE IP Core for Stratix® V Devices
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. IP Core Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices
2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.6. Clock Requirements for 40GBASE-KR4 Variations
2.7.7. External TX MAC PLL
2.7.8. Placement Settings for the LL 40GbE Core
2.8.2.1. Generating the LL 40GbE Testbench
2.8.2.2. Optimizing the IP Core Simulation With the Testbenches
2.8.2.3. Optimization in the 40GBASE-KR4 Testbench
2.8.2.4. Simulating with the Modelsim Simulator
2.8.2.5. Simulating with the NCSim Simulator
2.8.2.6. Simulating with the VCS Simulator
2.8.2.7. Testbench Output Example
3.2.1. LL 40GbE IP Core TX Datapath
3.2.2. LL 40GbE IP Core TX Data Bus Interfaces
3.2.3. LL 40GbE IP Core RX Datapath
3.2.4. LL 40GbE IP Core RX Data Bus Interfaces
3.2.5. External Reconfiguration Controller
3.2.6. External Transceiver PLL
3.2.7. External TX MAC PLL
3.2.8. Congestion and Flow Control Using Pause Frames
3.2.9. Pause Control and Generation Interface
3.2.10. Pause Control Frame Filtering
3.2.11. Link Fault Signaling Interface
3.2.12. Statistics Counters Interface
3.2.13. 1588 Precision Time Protocol Interfaces
3.2.14. PHY Status Interface
3.2.15. Transceiver PHY Serial Data Interface
3.2.16. Low Latency 40GBASE-KR4 IP Core Variations
3.2.17. Control and Status Interface
3.2.18. Arria 10 Transceiver Reconfiguration Interface
3.2.19. Clocks
3.2.20. Resets
3.2.2.1. LL 40GbE IP Core User Interface Data Bus
3.2.2.2. LL 40GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. LL 40GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. LL 40GbE IP Core RX Filtering
3.2.3.2. LL 40GbE IP Core Preamble Processing
3.2.3.3. IP Core Strict SFD Checking
3.2.3.4. LL 40GbE IP Core FCS (CRC-32) Removal
3.2.3.5. LL 40GbE IP Core CRC Checking
3.2.3.6. LL 40GbE IP Core Malformed Packet Handling
3.2.3.7. RX CRC Forwarding
3.2.3.8. Inter-Packet Gap
3.2.3.9. Pause Ignore
3.2.3.10. Control Frame Identification
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4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the Intel® Quartus® Prime software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a Signal Tap file with probe points matching your design hierarchy.
The Intel® Quartus® Prime software stores these files in the <IP core directory>/synth/debug/stp/ directory.
Synthesize your design using the Intel® Quartus® Prime software.
- To open the Tcl console, click View > Utility Windows > Tcl Console.
- Type the following command in the Tcl console:
source <IP core directory>/synth/debug/stp/build_stp.tcl
- To generate the STP file, type the following command:
main -stp_file <output stp file name>.stp -xml_file <input xml_file name>.xml -mode build
- To add this Signal Tap file (.stp) to your project, select Project > Add/Remove Files in Project. Then, compile your design.
- To program the FPGA, click Tools > Programmer.
- To start the Signal Tap Logic Analyzer, click Quartus Prime > Tools > Signal Tap Logic Analyzer.
The software generation script may not assign the Signal Tap acquisition clock in <output stp file name>.stp. Consequently, the Intel® Quartus® Prime software automatically creates a clock pin called auto_stp_external_clock. You may need to manually substitute the appropriate clock signal as the Signal Tap sampling clock for each STP instance.
- Recompile your design.
- To observe the state of your IP core, click Run Analysis.
You may see signals or Signal Tap instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances. They are present because software generates wider buses and some instances that your design does not include.