JESD204B Intel® FPGA IP Release Notes

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ID 683737
Date 7/19/2024
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v20.2.1 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.2.0 1.4. JESD204B Intel FPGA IP v19.1 1.5. JESD204B Intel FPGA IP v18.1 1.6. JESD204B Intel FPGA IP v18.0 1.7. JESD204B IP Core v17.1 1.8. JESD204B IP Core v17.0 1.9. JESD204B IP Core v16.1 1.10. JESD204B IP Core v16.0 1.11. JESD204B IP Core v15.1 1.12. JESD204B IP Core v15.0 1.13. JESD204B IP Core v14.1 1.14. JESD204B Intel® FPGA IP User Guide Archives 1.15. JESD204B Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.11. JESD204B IP Core v15.1

Table 11.  v15.1 November 2015
Description Impact
Added data rate support of up to 13.5 Gbps for Arria 10 and 7.5 Gbps for Arria V GT/ST devices. —
Added a new selection for PCS Option parameter—Enabled PMA Direct. —
Changed the default value for RX Phase Compensation FIFO empty error enable (csr_pcfifo_empty_err_en) CSR to 0 (refer to the RX register map). Disables the interrupt when PC FIFO empty condition occurs.
Added Example Designs tab in the parameter editor that automatically generates both simulation and hardware example designs with the parameters you specify. —
Added a new design example—Nios II Control. The Altera JESD204B IP core now includes two design examples:
  • RTL State Machine Control (supports Arria V, Cyclone V, Stratix V, and Arria 10 devices only)
  • Nios II Control (supports Arria 10 devices only)
 The RTL State Machine Control is a legacy design example and is renamed in this release.
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