JESD204B Intel® FPGA IP Release Notes

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Date 7/19/2024
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v20.2.1 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.2.0 1.4. JESD204B Intel FPGA IP v19.1 1.5. JESD204B Intel FPGA IP v18.1 1.6. JESD204B Intel FPGA IP v18.0 1.7. JESD204B IP Core v17.1 1.8. JESD204B IP Core v17.0 1.9. JESD204B IP Core v16.1 1.10. JESD204B IP Core v16.0 1.11. JESD204B IP Core v15.1 1.12. JESD204B IP Core v15.0 1.13. JESD204B IP Core v14.1 1.14. JESD204B Intel® FPGA IP User Guide Archives 1.15. JESD204B Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.12. JESD204B IP Core v15.0

Table 12.  v15.0 May 2015
Description Impact
Added support for Cyclone V FPGA device family (up to 5 Gbps). –
Added new parameters:
  • Enable Capability Registers
  • Set user-defined IP identifier
  • Enable Control and Status Registers
  • Enable Prbs Soft Accumulators
  • Enable manual F configuration
–
Added new register bits to support error detection (refer to New Register Bits).

These new register bits are available when you upgrade the IP core to v15.0.

Table 13.  New Register Bits
Register Bit Description
tx_err (0x60) csr_pll_locked_err Detects and flags an error when one or more lanes of PLL locked loses lock while the JESD204B link is running.
csr_pcfifo_full_err Detects and flags an error when one or more lanes of the Phase Compensation FIFO is unexpectedly full while the JESD204B link is running.
csr_pcfifo_empty_err Detects and flags an error when one or more lanes of the Phase Compensation FIFO is unexpectedly empty while the JESD204B link is running.
tx_err_enable (0x64) csr_pll_locked_err_en Enable interrupt for PLL lose lock error.
csr_pcfifo_full_err_en Enable interrupt for Phase Compensation FIFO full error.
csr_pcfifo_empty_err_en Enable interrupt for Phase Compensation FIFO empty error.
rx_err0 (0x60) csr_rx_locked_to_data_err Detects and flags an error when one or more lanes is not locked to data while the JESD204B link is running.
csr_pcfifo_full_err Detects and flags an error when one or more lanes of the Phase Compensation FIFO is unexpectedly full while the JESD204B link is running.
csr_pcfifo_empty_err Detects and flags an error when when one or more lanes of the Phase Compensation FIFO is unexpectedly empty while the JESD204B link is running.
rx_err_enable (0x74) csr_rx_locked_to_data_err_en Enable interrupt for RX not locked to data error.
csr_pcfifo_full_err_en Enable interrupt for Phase Compensation FIFO full error.
csr_pcfifo_empty_err_en Enable interrupt for Phase Compensation FIFO empty error.
rx_err_link_reinit (0x78) csr_rx_locked_to_data_err_link_reinit Enable link reinitialization for RX not locked to data error.
csr_pcfifo_full_err_link_reinit Enable link reinitialization for Phase Compensation FIFO full error.
csr_pcfifo_empty_err_link_reinit Enable link reinitialization for Phase Compensation FIFO empty error.
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